Cycle time reduction in data preparation
The present disclosure provides for methods of reducing cycle time in data preparation. In one embodiment, a method includes receiving an initial integrated circuit (IC) design layout and an optical proximity correction (OPC)-processed initial IC design layout, and receiving a revised IC design layout. The method further includes comparing the revised IC design layout to the initial IC design layout to identify a difference region of the revised IC design layout from the initial IC design layout, performing an OPC on the difference region of the revised IC design layout, and merging the OPC-processed difference region of the revised IC design layout with the OPC-processed initial IC design layout.
1. A method of reducing cycle time in data preparation, the method comprising:
receiving an initial integrated circuit (IC) design layout and an optical proximity correction (OPC)-processed initial IC design layout;
receiving a revised IC design layout;
comparing, by a processor, the revised IC design layout to the initial IC design layout to identify a difference region of the revised IC design layout from the initial IC design layout;
performing, by a processor, an OPC on the difference region of the revised IC design layout; and
merging, by a processor, the OPC-processed difference region of the revised IC design layout with the OPC-processed initial IC design layout.
2. The method of claim 1 , wherein the revised IC design layout is compared to the initial IC design layout by an exclusive or (XOR) logical operation.
3. The method of claim 1 , wherein the OPC performed on the difference region of the revised IC design layout is a rule-based OPC, a model-based OPC, or a combination thereof.
4. The method of claim 1 , further comprising determining a ratio of an area of the difference region and an area of the revised IC design layout.
5. The method of claim 4 , wherein the OPC on the difference region of the revised IC design layout is performed if the ratio is below a threshold.
6. The method of claim 1 , further comprising:
identifying a difference region of the initial IC design layout from the revised IC design layout; and
removing the difference region of the initial IC design layout from the OPC-processed initial IC design layout.
7. The method of claim 1 , further comprising:
performing an alignment check of a boundary patch around the merged difference region of the revised IC design layout; and
performing a lithographic process check of the boundary patch.
8. The method of claim 1 , wherein merging the OPC-processed difference region of the revised IC design layout with the OPC-processed initial IC design layout provides a merged OPC-processed revised IC design layout, and
further comprising fracturing of the merged OPC-processed revised IC design layout.
9. A method of reducing cycle time in data preparation, the method comprising:
receiving an initial integrated circuit (IC) design layout and an optical proximity correction (OPC)-processed initial IC design layout;
receiving a revised IC design layout;
comparing, by a processor, the revised IC design layout to the initial IC design layout by an exclusive or (XOR) logical operation to identify a difference region of the revised IC design layout from the initial IC design layout;
performing, by a processor, an OPC on the difference region of the revised IC design layout;
merging, by a processor, the OPC-processed difference region of the revised IC design layout with the OPC-processed initial IC design layout to provide a merged OPC-processed revised IC design layout; and
fracturing the merged OPC-processed revised IC design layout.
10. The method of claim 9 , wherein the OPC performed on the difference region of the revised IC design layout is a rule-based OPC, a model-based OPC, or a combination thereof.
11. The method of claim 9 , further comprising determining a ratio of an area of the difference region and an area of the revised IC design layout.
12. The method of claim 11 , wherein the OPC on the difference region of the revised IC design layout is performed if the ratio is below a threshold.
13. The method of claim 9 , further comprising:
identifying a difference region of the initial IC design layout from the revised IC design layout; and
removing the difference region of the initial IC design layout from the OPC-processed initial IC design layout.
14. The method of claim 9 , further comprising:
performing an alignment check of a boundary patch around the merged difference region of the revised IC design layout; and
performing a lithographic process check of the boundary patch.
15. A non-transitory computer-readable medium having instructions embodied thereon, the instructions executable by a processor to perform a method comprising:
receiving an initial integrated circuit (IC) design layout and an optical proximity correction (OPC)-processed initial IC design layout;
receiving a revised IC design layout;
comparing the revised IC design layout to the initial IC design layout to identify a difference region of the revised IC design layout from the initial IC design layout;
performing an OPC on the difference region of the revised IC design layout; and
merging the OPC-processed difference region of the revised IC design layout with the OPC-processed initial IC design layout.
16. The non-transitory computer-readable medium of claim 15 , wherein the revised IC design layout is compared to the initial IC design layout by an exclusive or (XOR) logical operation.
17. The non-transitory computer-readable medium of claim 15 , wherein the method further comprises:
determining a ratio of an area of the difference region and an area of the revised IC design layout; and
performing the OPC on the difference region of the revised IC design layout only if the ratio is below a threshold.
18. The non-transitory computer-readable medium of claim 15 , wherein the method further comprises:
identifying a difference region of the initial IC design layout from the revised IC design layout; and
removing the difference region of the initial IC design layout from the OPC-processed initial IC design layout.
19. The non-transitory computer-readable medium of claim 15 , wherein the method further comprises:
performing an alignment check of a boundary patch around the merged difference region of the revised IC design layout; and
performing a lithographic process check of the boundary patch.
20. The non-transitory computer-readable medium of claim 15 , wherein merging the OPC-processed difference region of the revised IC design layout with the OPC-processed initial IC design layout provides a merged OPC-processed revised IC design layout, and
wherein the method further comprises fracturing of the merged OPC-processed revised IC design layout.