IP Library Granted Patent US 8,460,970
Granted Patent B1
US 8,460,970 · App. 13/715,660 · Granted Jun 11, 2013

Lead frame ball grid array with traces under die having interlocking features

Inventor: Saravuth Sirinorakul (Bangkok, TH)
Assignee: UTAC Thai Limited
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Quick Facts
Patent No.
US 8,460,970
App. No.
13/715,660
Granted
Jun 11, 2013
Kind
B1
Abstract

A package includes a first plated area, a second plated area, a die attached to the first plated area, and a bond coupling the die to the second plated area. The package further includes a molding encapsulating the die, the bond, and the top surfaces of the first and second plated areas, such that the bottom surfaces of the first and second plated areas are exposed exterior to the package. Additional embodiments include a method of making the package.

Claims (15)

1. A method of making a packaged semiconductor device comprising:

a. etching a pattern of interlocking features on a top surface of a monolithic substrate;

b. plating a first pattern on the top surface of the monolithic substrate thereby forming a plurality of routing traces each having a first contact point and at least one additional contact point, wherein at least some of the first contact points or additional contact points coincide with at least one interlocking feature;

c. plating a second pattern on a bottom surface of a monolithic substrate;

d. mounting a semiconductor die on the top surface of the monolithic substrate with an adhesive;

e. attaching wirebonds from the semiconductor die to the first contact points of the routing traces;

f. encapsulating the die in a mold compound;

g. Etching away the portions of the monolithic substrate not plated by the second pattern thereby forming standoffs disposed at least some of the additional contact points; and

h. singulating the semiconductor device.

2. The method of claim 1 wherein the mold compound fills at least one of the interlocking features.

3. The method of claim 1 wherein the adhesive fills at least one of the interlocking features.

4. The method of claim 1 wherein the first pattern comprises any among a list of gold, silver, nickel, palladium and any alloy combination thereof.

5. The method of claim 1 wherein the plating a first pattern comprises arranging the first pattern such that the routing traces are disposed under the semiconductor die.

6. The method of claim 1 further comprising metallizing any exposed portion of the standoffs.

7. The method of claim 1 further comprising forming an underfill layer for encapsulating at least a portion of the standoffs.

Assignments (3)
CORRECTIVE ASSIGNMENT TO ADD THE ANNEX A AND THE ANNEX B WHICH WAS INADVERTENTLY LEFTOUT IN THE ORIGINAL ASSIGNMENT DOCUMENT PREVIOUSLY RECORDED ON REEL 037959 FRAME 0937. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Jul 8, 2016
From: UTAC THAI LIMITED
To: UTAC HEADQUARTERS PTE. LTD.
Reel/Frame 039902/0302 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 1, 2016
From: UTAC THAI LIMITED
To: UTAC HEADQUARTERS PTE. LTD.
Reel/Frame 037959/0937 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 14, 2012
From: SIRINORAKUL, SARAVUTH
To: UTAC THAI LIMITED
Reel/Frame 029475/0445 →
Continuity (6)
Continuation In Part 13080512 · Apr 5, 2011
Continuation In Part 11731522 · Mar 30, 2007
Continuation In Part 13040112 · Mar 3, 2011
Provisional Application 61455881 · Oct 27, 2010
Provisional Application 60795929 · Apr 28, 2006
Provisional Application 61321060 · Apr 5, 2010