Semiconductor device
A semiconductor device with a novel structure in which stored data can be retained even when power is not supplied, and does not have a limitation on the number of write cycles. The semiconductor device includes a memory cell including a first transistor, a second transistor, and an insulating layer placed between a source region or a drain region of the first transistor and a channel formation region of the second transistor. The first transistor and the second transistor are provided to at least partly overlap with each other. The insulating layer and a gate insulating layer of the second transistor satisfy the following formula: (t a /t b )×(∈ ra /∈ rb )<0.1, where t a represents the thickness of the gate insulating layer, t b represents the thickness of the insulating layer, ∈ ra represents the dielectric constant of the gate insulating layer, and ∈ rb represents the dielectric constant of the insulating layer.
1. A semiconductor device comprising:
a memory cell comprising:
a first transistor including:
a first channel formation region;
a first gate insulating layer over the first channel formation region;
a first gate electrode over the first gate insulating layer, wherein the first gate electrode overlaps with the first channel formation region; and
a source region and a drain region, wherein the first channel formation region is interposed between the source region and the drain region;
a second transistor including:
a second channel formation region;
a source electrode and a drain electrode which are electrically connected to the second channel formation region;
a second gate electrode over the second channel formation region; and
a second gate insulating layer between the second channel formation region and the second gate electrode; and
an insulating layer between the second channel formation region and one of the source region and the drain region,
wherein the first transistor and the second transistor overlap with each other at least partly, and
wherein the second gate insulating layer and the insulating layer satisfy a formula:
t
a
t
b
·
ɛ
rb
ɛ
ra
<
0.1
wherein t a represents a thickness of the second gate insulating layer, t b represents a thickness of the insulating layer, ∈ ra represents a dielectric constant of the second gate insulating layer, and ∈ rb represents a dielectric constant of the insulating layer.
2. The semiconductor device according to claim 1 , wherein the first gate electrode is electrically connected to one of the source electrode and the drain electrode.
3. The semiconductor device according to claim 1 , wherein a capacitor is constituted by the second gate insulating layer, a conductive layer, and one of the source electrode and the drain electrode.
4. The semiconductor device according to claim 1 ,
wherein the first channel formation region includes a first semiconductor material,
wherein the second channel formation region include a second semiconductor material, and
wherein the first semiconductor material and the second semiconductor material are different from each other.
5. The semiconductor device according to claim 1 , wherein the second channel formation region includes an oxide semiconductor.
6. A semiconductor device comprising:
a memory cell comprising:
a first transistor including:
a first channel formation region;
a first gate insulating layer over the first channel formation region;
a first gate electrode over the first gate insulating layer, wherein the first gate electrode overlaps with the first channel formation region; and
a source region and a drain region, wherein the first channel formation region is interposed between the source region and the drain region;
a second transistor including:
a second channel formation region;
a source electrode and a drain electrode which are electrically connected to the second channel formation region;
a second gate electrode over the second channel formation region; and
a second gate insulating layer between the second channel formation region and the second gate electrode; and
an insulating layer between the second channel formation region and one of the source region and the drain region,
wherein the first transistor and the second transistor overlap with each other at least partly, and
wherein the second gate insulating layer and the insulating layer satisfy a formula:
V
th
-
V
max
·
t
a
t
b
·
ɛ
rb
ɛ
ra
>
0
wherein t a represents a thickness of the second gate insulating layer, t b represents a thickness of the insulating layer, ∈ ra represents a dielectric constant of the second gate insulating layer, ∈ rb represents a dielectric constant of the insulating layer, V max represents a potential of one of the source region and the drain region, and V th represents a threshold voltage of the second transistor.
7. The semiconductor device according to claim 6 , wherein the first gate electrode is electrically connected to one of the source electrode and the drain electrode.
8. The semiconductor device according to claim 6 , wherein a capacitor is constituted by the second gate insulating layer, a conductive layer, and one of the source electrode and the drain electrode.
9. The semiconductor device according to claim 6 ,
wherein the first channel formation region includes a first semiconductor material,
wherein the second channel formation region include a second semiconductor material, and
wherein the first semiconductor material and the second semiconductor material are different from each other.
10. The semiconductor device according to claim 6 , wherein the second channel formation region includes an oxide semiconductor.
11. A semiconductor device comprising:
a memory cell comprising:
a first transistor including:
a first channel formation region;
a first gate insulating layer over the first channel formation region;
a first gate electrode over the first gate insulating layer, wherein the first gate electrode overlaps with the first channel formation region; and
a source region and a drain region, wherein the first channel formation region is interposed between the source region and the drain region;
a second transistor including:
a second channel formation region;
a source electrode and a drain electrode which are electrically connected to the second channel formation region;
a second gate electrode over the second channel formation region; and
a second gate insulating layer between the second channel formation region and the second gate electrode; and
an insulating layer between the second channel formation region and one of the source region and the drain region,
wherein the first transistor and the second transistor overlap with each other at least partly,
wherein a part of the source electrode and a part of the drain electrode are provided over the second channel formation region, and
wherein the second gate insulating layer and the insulating layer satisfy a formula:
t
a
t
b
·
ɛ
rb
ɛ
ra
<
0.1
wherein t a represents a thickness of the second gate insulating layer, t b represents a thickness of the insulating layer, ∈ ra represents a dielectric constant of the second gate insulating layer, and ∈ rb represents a dielectric constant of the insulating layer.
12. The semiconductor device according to claim 11 , wherein the first gate electrode is electrically connected to one of the source electrode and the drain electrode.
13. The semiconductor device according to claim 11 , wherein a capacitor is constituted by the second gate insulating layer, a conductive layer, and one of the source electrode and the drain electrode.
14. The semiconductor device according to claim 11 ,
wherein the first channel formation region includes a first semiconductor material,
wherein the second channel formation region include a second semiconductor material, and
wherein the first semiconductor material and the second semiconductor material are different from each other.
15. The semiconductor device according to claim 11 , wherein the second channel formation region includes an oxide semiconductor.