Semiconductor device and method of fabricating same
A semiconductor device having a core device with a high-k gate dielectric and an I/O device with a silicon dioxide or other non-high-k gate dielectric, and a method of fabricating such a device. A core well and an I/O well are created in a semiconductor substrate and separated by an isolation structure. An I/O device is formed over the I/O well and has a silicon dioxide or a low-k gate dielectric. A resistor may be formed on an isolation structure adjacent to the core well. A core-well device such as a transistor is formed over the core well, and has a high-k gate dielectric. In some embodiments, a p-type I/O well and an n-type I/O well are created. In a preferred embodiment, the I/O device or devices are formed prior to forming the core device and protected with a sacrificial layer until the core device is fabricated.
1. A semiconductor device comprising:
a core device on a substrate, the core device comprising a high-k gate dielectric disposed over a strained-silicon channel region, wherein the strained-silicon channel region is set into a recess of the substrate; and
a resistor located over an isolation region, the isolation region extending into the substrate; and
an I/O device, wherein the I/O device does not include a high-k gate dielectric.
2. The semiconductor device of claim 1 , wherein the strained-silicon channel region comprises a silicon layer over a silicon-germanium layer.
3. The semiconductor device of claim 2 , wherein the core device further comprises source/drain regions, wherein the silicon layer and the silicon germanium layer do not extend into the source/drain regions of the core device.
4. The semiconductor device of claim 1 , wherein the core device further comprises source/drain regions, the source/drain regions having an upper boundary that extends above the high-k gate dielectric.
5. The semiconductor device of claim 1 , wherein the isolation region comprises a shallow trench isolation.
6. A semiconductor device comprising:
a dielectric material extending into a substrate;
a resistor located over the dielectric material;
a core device on the substrate, the core device comprising:
a gate dielectric over the substrate, the gate dielectric comprising a high-k material; and
a strained-silicon channel region located beneath the gate dielectric and within a recess of the substrate; and
an I/O device, wherein the I/O device does not comprise a high-k material.
7. The semiconductor device of claim 6 , wherein the strained-silicon channel region comprises a layer of silicon-germanium and a layer of silicon overlying the layer of silicon-germanium.
8. The semiconductor device of claim 7 , wherein the layer of silicon and the layer of silicon-germanium do not extend into source/drain regions of the core device.
9. The semiconductor device of claim 6 , wherein the core device further comprises source/drain regions that extend above the gate dielectric.
10. The semiconductor device of claim 6 , wherein the resistor comprises polysilicon.
11. The semiconductor device of claim 6 , wherein the dielectric material is part of a shallow trench isolation.
12. A semiconductor device comprising:
a resistor formed over an isolation structure, wherein the isolation structure extends into a substrate;
a core device, the core device comprising a high-k dielectric material, the high-k dielectric material located over a strained-silicon channel region, wherein the strained-silicon channel region is located within an opening of the substrate; and
an I/O device, wherein the I/O device has a gate dielectric free from high-k dielectric material.
13. The semiconductor device of claim 12 , wherein the strained-silicon channel region comprises a silicon layer over a silicon-germanium layer.
14. The semiconductor device of claim 13 , wherein the core device further comprises source/drain regions, and wherein the silicon layer and the silicon germanium layer do not extend into the source/drain regions of the core device.
15. The semiconductor device of claim 12 , wherein the core device further comprises source/drain regions having an upper boundary that extends above the high-k dielectric material.
16. The semiconductor device of claim 12 , wherein the isolation structure is a shallow trench isolation.
17. The semiconductor device of claim 12 , wherein the resistor comprises polysilicon.