Method and system for managing sleep states of interrupt controllers in a portable computing device

1. A method for managing sleep states of one or more interrupt controllers of processors contained within a portable computing device comprising:

defining wake-up interrupt settings in a storage device contained within the portable computing device;

generating an alert that wake-up settings in the storage device have been defined;

reviewing wake-up interrupt settings in the storage device for a plurality of interrupt controllers that correspond with a plurality of processors contained within the portable computing device;

merging the wake-up settings in the storage device; and

sending the merged wake-up settings to a power manager responsible for issuing signals to place interrupt controllers into a sleep state.

2. The method of claim 1 , further comprising reviewing a permissions table to determine if a processor has authority to change the state of an interrupt controller.

3. The method of claim 1 , further comprising sending the merged wake-up settings to a plurality of registers within the power manager.

4. The method of claim 1 , wherein the wake-up settings comprise at least one of an enable setting, a type/detect setting, a polarity setting, a status setting, and a clear setting.

5. The method of claim 1 , wherein the storage device comprises memory elements which mirror registers contained within the power manager.

6. The method of claim 1 , further comprising relaying signals from the power manager to a power management integrated circuit (PMIC).

7. The method of claim 1 , further comprising sending an interrupt signal from the power manager to a processor.

8. The method of claim 1 , further comprising reviewing a portion of the storage device assigned to a particular processor for wake-up settings.

9. The method of claim 8 , further comprising translating the wake-up settings from the storage device using a local interrupt table.

10. The method of claim 9 , further comprising transmitting the translated wake-up settings to an interrupt controller of the particular processor.

11. A computer system for managing sleep states of one or more interrupt controllers of contained within a portable computing device, the system comprising:

a processing element operable to:

define wake-up interrupt settings in a storage device contained within the portable computing device;

generate an alert that wake-up settings in the storage device have been defined;

review wake-up interrupt settings in the storage device for a plurality of interrupt controllers that correspond with a plurality of processors contained within the portable computing device;

merge the wake-up settings in the storage device; and

send the merged wake-up settings to a power manager responsible for issuing signals to place interrupt controllers into a sleep state.

12. The system of claim 11 , wherein the processing element is further operable to:

review a permissions table to determine if a processor has authority to change the state of an interrupt controller.

13. The system of claim 11 , wherein the processing element is further operable to:

send the merged wake-up settings to a plurality of registers within the power manager.

14. The system of claim 11 , wherein the wake-up settings comprise at least one of an enable setting, a type/detect setting, a polarity setting, a status setting, and a clear setting.

15. The system of claim 11 , wherein the storage device comprises memory elements which mirror registers contained within the power manager.

16. The system of claim 11 , wherein the processing element is further operable to:

relay signals from the power manager to a power management integrated circuit (PMIC).

17. The system of claim 11 , wherein the processing element is further operable to:

send an interrupt signal from the power manager to a processor.

18. The system of claim 11 , wherein the processing element is further operable to:

review a portion of the storage device assigned to a particular processor for wake-up settings.

19. The system of claim 18 , wherein the processing element is further operable to:

translate the wake-up settings from the storage device using a local interrupt table.

20. The system of claim 19 , wherein the processing element is further operable to:

transmit the translated wake-up settings to an interrupt controller of a processor.

21. A computer system for managing sleep states of one or more interrupt controllers of processors contained within a portable computing device, the system comprising:

means for defining wake-up interrupt settings in a storage device contained within the portable computing device;

means for generating an alert that wake-up settings in the storage device have been defined;

means for reviewing wake-up interrupt settings in the storage device for a plurality of interrupt controllers that correspond with a plurality of processors contained within the portable computing device;

means for merging the wake-up settings in the storage device; and

means for sending the merged wake-up settings to a power manager responsible for issuing signals to place interrupt controllers into a sleep state.

22. The system of claim 21 , further comprising:

means for reviewing a permissions table to determine if a processor has authority to change the state of an interrupt controller.

23. The system of claim 21 , further comprising:

means for sending the merged wake-up settings to a plurality of registers within the power manager.

24. The system of claim 21 , wherein the wake-up settings comprise at least one of an enable setting, a type/detect setting, a polarity setting, a status setting, and a clear setting.

25. The system of claim 21 , wherein the storage device comprises memory elements which mirror registers contained within the power manager.

26. The system of claim 21 , further comprising:

means for relaying signals from the power manager to a power management integrated circuit (PMIC).

27. The system of claim 21 , further comprising:

means for sending an interrupt signal from the power manager to a processor.

28. The system of claim 21 , further comprising:

means for reviewing a portion of the storage device assigned to a particular processor for wake-up settings.

29. The system of claim 28 , further comprising means for translating the wake-up settings from the storage device using a local interrupt table.

30. The system of claim 29 , further comprising:

means for transmitting the translated wake-up settings to an interrupt controller of the particular processor.

31. A non-transitory processor readable storage medium having stored thereon processor-executable instructions configured to cause a processor to perform operations for managing sleep states of one or more interrupt controllers of processors contained within a portable computing device, said operations comprising:

defining wake-up interrupt settings in a storage device contained within the portable computing device;

generating an alert that wake-up settings in the storage device have been defined;

reviewing wake-up interrupt settings in the storage device for a plurality of interrupt controllers that correspond with a plurality of processors contained within the portable computing device;

merging the wake-up settings in the storage device; and

sending the merged wake-up settings to a power manager responsible for issuing signals to place interrupt controllers into a sleep state.

32. The non-transitory processor readable storage medium of claim 31 , wherein the stored processor-executable instructions are configured to cause the processor to perform operations further comprising:

reviewing a permissions table to determine if a processor has authority to change the state of an interrupt controller.

33. The non-transitory processor readable storage medium of claim 31 , wherein the stored processor-executable instructions are configured to cause the processor to perform operations further comprising:

sending the merged wake-up settings to a plurality of registers within the power manager.

34. The non-transitory processor readable storage medium, wherein the wake-up settings comprise at least one of an enable setting, a type/detect setting, a polarity setting, a status setting, and a clear setting.

35. The non-transitory processor readable storage medium, wherein the storage device comprises memory elements which mirror registers contained within the power manager.

36. The non-transitory processor readable storage medium of claim 31 , wherein the stored processor-executable instructions are configured to cause the processor to perform operations further comprising:

relaying signals from the power manager to a power management integrated circuit (PMIC).

37. The non-transitory processor readable storage medium of claim 31 , wherein the stored processor-executable instructions are configured to cause the processor to perform operations further comprising:

sending an interrupt signal from the power manager to a processor.

38. The non-transitory processor readable storage medium of claim 31 , wherein the stored processor-executable instructions are configured to cause the processor to perform operations further comprising:

reviewing a portion of the storage device assigned to a particular processor for wake-up settings.

39. The non-transitory processor readable storage medium of claim 38 , wherein the stored processor-executable instructions are configured to cause the processor to perform operations further comprising:

translating the wake-up settings from the storage device using a local interrupt table.

40. The non-transitory processor readable storage medium of claim 39 , wherein the stored processor-executable instructions are configured to cause the processor to perform operations further comprising:

transmitting the translated wake-up settings to an interrupt controller of the particular processor.