Address caching stored translation
Systems and/or methods that facilitate logical block address (LBA) to physical block address (PBA) translations associated with a memory component(s) are presented. The disclosed subject matter employs an optimized block address (BA) component that can facilitate caching the LBA to PBA translations within a memory controller component based in part on a predetermined optimization criteria to facilitate improving the access of data associated with the memory component. The predetermined optimization criteria can relate to a length of time since an LBA has been accessed, a number of times the LBA has been access, a data size of data related to an LBA, and/or other factors. The LBA to PBA translations can be utilized to facilitate accessing the LBA and/or associated data using the cached translation, instead of performing various functions to determine the translation.
1. A system that facilitates physical block address (PBA) and logical block address (LBA) translation in at least one memory component, comprising:
the at least one memory component configured to execute at least one memory operation and includes a plurality of memory locations,
a memory controller component configured to store LBA to PBA translations respectively associated with a subset of LBAs based in part on a predefined optimization criteria, wherein the optimization criteria comprises at least a number of times an LBA is presented to the memory controller component in association with the at least one memory operation;
a defrag component configured to defragment a chunk of data having portions of data that are stored in nonconsecutive pages associated with the at least one memory component and store the portions of data in consecutive pages associated with the at least one memory component during time periods that overlap with execution of the at least one memory operation; and
a block address cache component (BA cache component) configured to store LBA to PBA translation information associated with at least one LBA used to access the at least one memory component,
wherein the defrag component reduces a size of the BA cache component that is associated with storage of the LBA to PBA translation information by aligning the portions of data in consecutive page locations and storing, in the BA cache component, a starting PBA page number associated with an LBA or a number of pages value.
2. The system of claim 1 , the memory controller component facilitates determining attributes associated with an LBA to facilitate determining an LBA to PBA translation to facilitate access of the LBA or data associated therewith, wherein the memory controller component is configured to store an LBA to PBA translation when a number of times the LBA has been accessed meets or exceeds a number.
3. The system of claim 1 , wherein the memory controller component retrieves the portions of data associated with the chunk of data without requiring separate PBA page information for each portion of the chunk of data.
4. The system of claim 1 , further comprising a block address counter component (BA counter component) that tracks and stores information related to a number of times the at least one LBA is presented to the memory controller component in association with the at least one memory operation.
5. The system of claim 1 , further comprising a block address timer component (BA timer component) that stores time information related to an amount of time that has passed since the at least one LBA has been presented to the memory controller component to perform the at least one memory operation.
6. The system of claim 5 , the BA timer component utilizes at least one of a monotonically incrementing clock, a time stamp, or a clock that tracks time based in part on clock cycles associated with the memory controller component, or a combination thereof, to facilitate obtaining time information respectively associated with LBAs.
7. The system of claim 1 , wherein the predefined optimization criteria further includes at least one of: an amount of time that has passed since the an LBA was presented to the memory controller component in association with a memory operation, a number of times within a predetermined period of time that a LBA was presented to the memory controller component in association with the at least one memory operation, or a size of data associated with a LBA that is presented to the memory controller component in association with the at least one memory operation.
8. The system of claim 1 , wherein the defrag component performs a search of the at least one memory component to determine if chunks of data are stored in two or more nonconsecutive pages associated with the at least one memory component.
9. The system of claim 8 , wherein the defrag component works in conjunction with a wear leveling component to determine where the chunks of data are to be stored in consecutive pages associated with the at least one memory component.
10. The system of claim 8 , further comprising an optimized block address lookup component (BA lookup component) that facilitates the storage of a number of pages that is associated with the LBA to PBA translation information that corresponds to the number of consecutive pages in which the chunks of data are stored.
11. An electronic device that facilitates physical block address (PBA) and logical block address (LBA) translation in at least one memory component, comprising:
the at least one memory component configured to execute at least one memory operation and includes a plurality of memory locations,
a memory controller component configured to store LBA to PBA translations respectively associated with a subset of LBAs based in part on a predefined optimization criteria, wherein the optimization criteria comprises at least a number of times an LBA is presented to the memory controller component in association with the at least one memory operation;
a defrag component configured to defragment a chunk of data having portions of data that are stored in nonconsecutive pages associated with the at least one memory component and store the portions of data in consecutive pages associated with the at least one memory component during time periods that overlap with execution of the at least one memory operation; and
a block address cache component (BA cache component) configured to store LBA to PBA translation information associated with at least one LBA used to access the at least one memory component,
wherein the defrag component reduces a size of the BA cache component that is associated with storage of the LBA to PBA translation information by aligning the portions of data in consecutive page locations and storing, in the BA cache component, a starting PBA page number associated with an LBA or a number of pages value.
12. The electronic device of claim 11 , wherein the electronic device is one of a computer, a laptop computer, a router, an access point, a media player, a media recorder, an audio player, an audio recorder, a video player, a video recorder, a television, a smart card, a phone, a cellular phone, a smart phone, an electronic organizer, a personal digital assistant (PDA), a portable email reader, a digital camera, an electronic game, an electronic device associated with digital rights management, a Personal Computer Memory Card International Association (PCMCIA) card, a trusted platform module (TPM), a Hardware Security Module (HSM), a set-top box, a digital video recorder, a gaming console, a navigation device, a secure memory device with computational capabilities, a device with at least one tamper-resistant chip, an electronic device associated with an industrial control system, or an embedded computer in a machine, the machine comprising at least one of an airplane, a copier, a motor vehicle, or a microwave oven.