IP Library › Granted Patent US 8,464,123
Granted Patent B2
US 8,464,123 · App. 12/774,746 · Granted Jun 11, 2013

Matrix structure for block encoding

Inventors: Idan Alrod (Herzliya, IL); Eran Sharon (Rishon Lezion, IL); Simon Litsyn (Givat Shmuel, IL)
Assignee: Ramot At Tel Aviv University Ltd.
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Quick Facts
Patent No.
US 8,464,123
App. No.
12/774,746
Granted
Jun 11, 2013
Kind
B2
Abstract

A plurality of information bits are encoded using a parity-check matrix that is equivalent to a modular code matrix. The modular code matrix is a diagonal sub-matrix structure immediately above a connection layer that includes a plurality of diverse connection layer sub-matrices, all but at most one of which are below corresponding diagonal matrix structure sub-matrices. The information bits are assembled with a plurality of parity bits produced by the encoding to provide a codeword that is exported to a medium. Preferably, all the diagonal matrix structure sub-matrices are identical. Preferably, some of the parity bits are computed using only diagonal matrix structure sub-matrices.

Claims (45)

1. A method of encoding and exporting a plurality of information bits, comprising:

(a) providing a parity-check matrix that is equivalent to a modular code matrix that consists of a diagonal sub-matrix structure, including a plurality of diagonal structure sub-matrices, immediately above a connection layer that includes a plurality of contiguous diverse connection layer sub-matrices that have the same number of rows, with all but at most one of the connection layer sub-matrices being below corresponding diagonal structure sub-matrices;

(b) using the information bits and the parity-check matrix to compute, via an encoder, a plurality of parity bits;

(c) assembling, via the encoder, the information bits and the parity bits to form a codeword; and

(d) exporting at least a portion of the codeword to a medium.

2. The method of claim 1 , wherein all the diagonal structure sub-matrices are identical.

3. The method of claim 1 , wherein a number of non-zero elements in each diagonal structure sub-matrix is at most a predefined fraction of a number of elements of the each diagonal structure sub-matrix.

4. The method of claim 1 , wherein only at least a portion of the diagonal structure sub-matrices are used to compute a portion of the parity bits.

5. The method of claim 4 , wherein each diagonal structure sub-matrix of the at least portion of the diagonal structure sub-matrices is used separately to compute only a respective at least one of the parity bits.

6. The method of claim 1 , wherein each connection layer sub-matrix is below a corresponding diagonal structure sub-matrix.

7. The method of claim 1 , wherein every connection layer sub-matrix except for a rightmost connection layer sub-matrix is below a corresponding diagonal structure sub-matrix.

8. The method of claim 1 , wherein each connection layer sub-matrix is of the form [IZ]Q, where I is an identity matrix, Z is a zero matrix and Q is a pseudorandom permutation matrix.

9. The method of claim 1 , wherein the connection layer sub-matrices have non-zero elements only in pre-defined columns of the modular code matrix.

10. The method of claim 9 , wherein the pre-defined columns correspond to at least a portion of the parity bits.

11. The method of claim 10 , wherein the pre-defined columns correspond to only a portion of the parity bits, and wherein all of the codeword except the portion of the parity bits is exported to the medium.

12. The method of claim 1 , wherein the parity check matrix is identical to the modular code matrix.

13. The method of claim 1 , wherein the parity check matrix is the modular code matrix left-multiplied by an invertible matrix and right-multiplied by a first permutation matrix.

14. The method of claim 13 , wherein the invertible matrix is a second permutation matrix.

15. The method of claim 13 , wherein the modular code matrix is embedded in the parity-check matrix.

16. An apparatus for encoding and exporting a plurality of information bits, comprising:

(a) an encoder for encoding the plurality of information bits by:

(i) using the information bits and a parity-check matrix to compute a plurality of parity bits, wherein the parity-check matrix is equivalent to a modular code matrix that consists of a diagonal sub-matrix structure, including a plurality of diagonal structure sub-matrices, immediately above a connection layer that includes a plurality of contiguous diverse connection layer sub-matrices that have the same number of rows, with all but at most one of the connection layer sub-matrices being below corresponding diagonal structure sub-matrices, and

(ii) assembling the information bits and the parity bits to form a codeword; and

(b) a mechanism for exporting at least a portion of the codeword to a medium.

17. The apparatus of claim 16 , wherein the medium is a storage medium.

18. The apparatus of claim 17 , wherein the apparatus is a controller of the storage medium.

19. The apparatus of claim 17 , wherein the apparatus is a host of the storage medium.

20. The apparatus of claim 16 , wherein the medium is a transmission medium.

21. A transmitter comprising the apparatus of claim 20 .

22. The transmitter of claim 21 , wherein the mechanism includes a modulator that transmits the at least portion of the codeword as a modulated signal.

23. A memory device comprising:

(a) the apparatus of claim 18 ; and

(b) the storage medium of claim 18 .

24. A system comprising:

(a) the apparatus of claim 19 ; and

(b) the storage medium of claim 19 .

25. A non-transitory computer-readable storage medium having embodied thereon computer-readable code for managing a memory, the computer-readable code comprising:

(a) program code for using a parity-check matrix to compute a plurality of parity bits, wherein the parity-check matrix is equivalent to a modular code matrix that consists of a diagonal sub-matrix structure, including a plurality of diagonal structure sub-matrices, immediately above a connection layer that includes a plurality of contiguous diverse connection layer sub-matrices that have the same number of rows, with all but at most one of the connection layer sub-matrices being below corresponding diagonal structure sub-matrices;

(b) program code for assembling the information bits and the parity bits to form a codeword; and

(c) program code for storing the codeword in the memory.

26. A system comprising:

(a) a memory; and

(b) a host, of the memory, that includes:

(i) the computer-readable storage medium of claim 25 , and

(ii) a processor for executing the computer-readable code.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 6, 2010
From: ALROD, IDAN; SHARON, ERAN; LITSYN, SIMON
To: RAMOT AT TEL AVIV UNIVERSITY LTD.
Reel/Frame 024345/0138 →
Continuity (2)
Provisional Application 61176123 · May 7, 2009
Related Publication 20100287440A1 · Nov 11, 2010