Power domain controller with gated through silicon via having FET with horizontal channel
A semiconductor chip has a gated through silicon via (TSVG). The TSVG may be switched so that the TSVG can be made conducting or non-conducting. The semiconductor chip may be used between a lower level semiconductor chip and a higher semiconductor chip to control whether a voltage supply on the lower level semiconductor chip is connected to or disconnected from a voltage domain in the upper level semiconductor chip. The TSVG comprises an FET controlled by the lower level chip as a switch.
1. A method for making a gated through silicon via (TSVG) in a semiconductor chip comprising:
implanting a first implant area and a second implant area, the implanting extending from a top surface of the semiconductor chip to a bottom surface of the semiconductor chip;
creating a through silicon via hole (TSV hole) through the semiconductor chip, the TSV hole cutting through a portion of the first implant area and the second implant area;
creating a gate dielectric on an outer surface of the TSV hole while leaving a remaining portion of the TSV hole;
filling the remaining portion of the TSV hole with a TSV conductor.
2. The method for making the gated through TSVG in the semiconductor chip, wherein the implanting of the first implant area and the second implant area further comprises:
implanting a first implant dose in the first implant area and the second implant area using a first implant energy; and
implanting a second implant dose in the first implant area and in the second implant area using a second implant energy.