IP Library › Granted Patent US 8,466,494
Granted Patent B2
US 8,466,494 · App. 13/396,127 · Granted Jun 18, 2013

Field effect transistor, semiconductor switch circuit, and communication apparatus

Inventor: Shinichi Tamari (Kagoshima, JP)
Assignee: Sony Corporation
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,466,494
App. No.
13/396,127
Granted
Jun 18, 2013
Kind
B2
Abstract

A field effect transistor includes a source wiring that is formed on a compound semiconductor substrate, and has a plurality of source electrodes arranged in parallel to each other at predetermined intervals, a drain wiring that is formed on the compound semiconductor substrate, and has a plurality of drain electrodes arranged in parallel to each other at predetermined intervals and alternatively disposed in a parallel direction of the plurality of source electrodes, a gate wiring that is formed on the compound semiconductor substrate, and has a portion located between the source electrode and the drain electrode which are adjacent to each other at least in the parallel direction, and a plurality of buried gate layers that is formed under the gate wiring in a region in which the gate wiring is formed, and is independently provided between each electrode of the source electrodes and the drain electrodes.

Claims (15)

1. A field effect transistor, comprising:

a source wiring that is formed on a compound semiconductor substrate, and has a plurality of source electrodes arranged in parallel to each other at predetermined intervals;

a drain wiring that is formed on the compound semiconductor substrate, and has a plurality of drain electrodes arranged in parallel to each other at predetermined intervals and alternatively disposed in a parallel direction of the plurality of source electrodes;

a gate wiring that is formed on the compound semiconductor substrate, and has a portion located between the source electrode and the drain electrode which are adjacent to each other at least in the parallel direction; and

a plurality of buried gate layers that is formed under the gate wiring in a region in which the gate wiring is formed, and is independently provided between each electrode of the plurality of source electrodes and the plurality of drain electrodes.

2. The field effect transistor according to claim 1 , wherein

each of the plurality of buried gate layers is formed in a straight-line shape by a portion existing within an operation region on the compound semiconductor substrate including a portion in which the source electrode and the drain electrode overlap in the parallel direction between the source wiring and the drain wiring, and by a portion existing in a region other than the operation region, and

the portion existing in the region other than the operation region has a minimum length used to ensure operation in the operation region.

3. A semiconductor switch circuit comprising:

the field effect transistor according to claim 1 ; and

an input terminal connected to a gate of the field effect transistor through a resistance element,

wherein the field effect transistor is operated by a switching signal input to the input terminal.

4. A communication apparatus comprising:

the semiconductor switch circuit according to claim 3 ,

wherein the communication apparatus performs path switching of a signal by an operation of the semiconductor switch circuit.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 24, 2012
From: TAMARI, SHINICHI
To: SONY CORPORATION
Reel/Frame 028094/0822 →
Priority Claims (1)
JP 2011-036537 · Feb 23, 2011 · national
Continuity (1)
Related Publication 20120211802A1 · Aug 23, 2012