IP Library › Granted Patent US 8,470,621
Granted Patent B2
US 8,470,621 · App. 12/722,231 · Granted Jun 25, 2013

Method for fabricating a flip-chip semiconductor optoelectronic device

Inventors: Chester Kuo (Taipei, TW); Lung Hsin Chen (Hsinchu County, TW); Wen Liang Tseng (Hsinchu, TW); Shih Cheng Huang (Hsinchu, TW); Po Min Tu (Chiayi County, TW); Ying Chao Yeh (Taipei County, TW); Wen Yu Lin (Taichung County, TW); Peng Yi Wu (Taichung, TW); Shih Hsiung Chan (Hsinchu County, TW)
Assignee: Advanced Optoelectronic Technology, Inc.
H01L27/156
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Quick Facts
Patent No.
US 8,470,621
App. No.
12/722,231
Granted
Jun 25, 2013
Kind
B2
Abstract

A method for fabricating flip-chip semiconductor optoelectronic devices initially flip-chip bonds a semiconductor optoelectronic chip attached to an epitaxial substrate to a packaging substrate. The epitaxial substrate is then separated using lift-off technology.

Claims (25)

1. A method for fabricating a flip-chip semiconductor optoelectronic device, comprising the steps of:

providing an epitaxial substrate;

forming a sacrificial layer on said epitaxial substrate, which comprises steps of:

forming a first Group III nitride semiconductor layer on said epitaxial substrate;

forming a patterned mask on said first Group III nitride semiconductor layer;

etching said first Group III nitride semiconductor layer; and

removing said patterned mask;

forming a semiconductor light-emitting structure on said sacrificial layer, said semiconductor light-emitting structure including a first surface and a second surface opposite to the first surface of said semiconductor light-emitting structure, wherein said sacrificial layer is on said second surface of said semiconductor light-emitting structure;

forming an n-type electrode and a p-type electrode on said first surface of said semiconductor light-emitting structure;

flip chip bonding said semiconductor light-emitting structure to a packaging substrate including a first surface, a second surface opposite to said first surface of said packaging substrate, a first bond pad formed on said first surface of said packaging substrate, a second bond pad formed on said first surface of said packaging substrate, a first bump formed on said first bond pad, and a second bump formed on said second bond pad, wherein said n-type electrode is electrically attached to said first bump, and said p-type electrode is electrically attached to said second bump;

disposing a transparent adhesive material between said first surface of said packaging substrate and said first surface of said semiconductor light-emitting structure, enclosing said first bond pad, said second bond pad, said first bump, and said second bump; and

separating said epitaxial substrate by etching said sacrificial layer.

2. The method of claim 1 , wherein said epitaxial substrate is a sapphire substrate, a silicon carbide substrate, a lithium aluminate substrate, a lithium gallate substrate, a silicon substrate, a gallium nitride substrate, a zinc oxide substrate, an aluminum zinc oxide substrate, a gallium arsenide substrate, a gallium phosphide substrate, a gallium antimonide substrate, an indium phosphide substrate, an indium arsenide substrate, or a zinc selenide substrate.

3. The method of claim 1 , wherein said sacrificial layer is etched by a wet etch or dry etch, or said sacrificial layer is etched by employing an inductively coupled plasma etcher.

4. The method of claim 1 , wherein the material of said first and second bumps is palladium tin alloy.

5. The method of claim 1 , wherein the material of said n-type electrode is titanium/aluminum/titanium/gold alloy, chromium gold alloy or gold lead alloy.

6. The method of claim 1 , wherein the material of said p-type electrode is nickel gold alloy, platinum gold alloy, chromium gold alloy, tungsten or palladium.

7. The method of claim 1 , further comprising a step of forming a dielectric layer between said n-type electrode and said p-type electrode to increase the hardness of said semiconductor light-emitting structure and to electrically insulate said n-type electrode from said p-type electrode.

8. The method of claim 7 , wherein the material of said dielectric layer is silicon oxide, epoxy resin, silicon nitride, titanium oxide, or aluminum nitride.

9. The method of claim 1 , further comprising a step of forming a protecting layer around said semiconductor light-emitting structure, and said step of forming a protecting layer is performed before said step of separating said epitaxial substrate.

10. The method of claim 9 , wherein the material of said protecting layer is silicon oxide.

11. The method of claim 1 , wherein said step of separating said epitaxial substrate by etching said sacrificial layer is performed employing a wet etch method.

12. The method of claim 1 , wherein the material of said dielectric layer is silicon oxide, epoxy resin or silicon nitride.

13. The method of claim 1 , wherein said packaging substrate is a printed circuit board, a bismaleimide triazine resin printed circuit board, a metal core printed circuit board, a flexible printed circuit board, a ceramic substrate, or a silicon substrate.

14. The method of claim 1 , wherein the material of said semiconductor light-emitting structure is Group III-V compound semiconductor.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 11, 2010
From: KUO, CHESTER; CHEN, LUNG HSIN; TSENG, WEN LIANG; HUANG, SHIH CHENG; TU, PO MIN; YEH, YING CHAO; LIN, WEN YU; WU, PENG YI; CHAN, SHIH HSIUNG
To: ADVANCED OPTOELECTRONIC TECHNOLOGY INC.
Reel/Frame 024068/0499 →
Priority Claims (1)
TW 98108127 A · Mar 13, 2009 · national
Continuity (1)
Related Publication 20100230711A1 · Sep 16, 2010