Granted Patent B2

US 8,471,644 · App. 13/009,471 · Granted Jun 25, 2013

Inventors: Robert Thelen (Fort Collins, CO); Herman H. Pang (Fort Collins, CO)

Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.

Abstract

Claims (32)

1. A gain-control circuit, comprising:

a duty cycle detector having a first signal input coupled to a first output of a voltage-controlled oscillator, a second signal input coupled to a second output of the voltage-controlled oscillator, and an output, the duty cycle detector including a resistively loaded multiple stage pseudo NMOS inverter and arranged to generate an estimate of one of a first voltage present on the first signal input and a second voltage present on the second signal input;

an analog-to-digital converter having an input coupled to the output of the duty cycle detector and an N-bit bus, the analog-to-digital converter generating a representation of the estimate on the N-bit bus; and

a function generator coupled to the N-bit bus and arranged to receive a target value, the function generator configured to generate a corrected value as a function of the representation on the N-bit bus and to generate a control word in response to the corrected value and the target value.

2. The gain-control circuit of claim 1 , wherein the control word is coupled to current sources in the voltage-controlled oscillator.

3. The gain-control circuit of claim 2 , wherein the control word includes an integer number of bits corresponding in a one-to-one relationship with respective current sources coupled to the drains of transistors in the voltage-controlled oscillator.

4. The gain-control circuit of claim 1 , wherein the duty cycle detector is coupled to the voltage-controlled oscillator by a capacitor.

5. The gain-control circuit of claim 1 , wherein the duty cycle detector comprises an output filter that generates a DC voltage.

6. The gain-control circuit of claim 1 , wherein the function generator generates an amplitude as a function of a threshold voltage, a coupled voltage offset, and a target amplitude.

7. The gain-control circuit of claim 6 , wherein the threshold voltage is adjusted with a first replica circuit.

8. The gain-control circuit of claim 1 , wherein a measured value is determined as a function of a filtered DC voltage, a pseudo NMOS inverter low voltage level, and a supply voltage.

9. The gain-control circuit of claim 8 , wherein the pseudo NMOS inverter low voltage level is adjusted with a second replica circuit.

10. The gain-control circuit of claim 1 , wherein the function generator generates an amplitude in accordance with a trigonometric function.

11. A method for controlling the amplitude of a voltage-controlled oscillator coupled to a gain-control circuit, the method comprising:

using a duty cycle detector to generate an estimate of the amplitude of a voltage-controlled oscillator, wherein using the duty cycle detector includes using a multiple stage pseudo NMOS inverter;

generating a representation of the estimate of the amplitude of the voltage-controlled oscillator;

using the representation of the estimate of the amplitude of the voltage-controlled oscillator to generate a corrected estimate;

using the corrected estimate as an input to a function generator to determine a measured amplitude of the output of the voltage-controlled oscillator;

comparing the measured amplitude with a target amplitude to generate a control word; and

using the control word to enable current sources in the voltage-controlled oscillator.

12. The method of claim 11 , wherein using a duty cycle detector to generate an estimate of the amplitude of a voltage-controlled oscillator includes coupling the duty cycle detector to the voltage-controlled oscillator with a capacitor.

13. The method of claim 11 , wherein using a duty cycle detector to generate an estimate of the amplitude of a voltage-controlled oscillator includes using a resistor network to determine an AC-coupled voltage level.

14. The method of claim 11 , wherein using a duty cycle detector to generate an estimate of the amplitude of a voltage-controlled oscillator includes using a first replica circuit to adjust a threshold voltage.

15. The method of claim 11 , further comprising coupling an N th stage output of the multiple stage pseudo NMOS inverter to a filter to generate a filtered version of the estimate of the amplitude of the voltage-controlled oscillator.

16. The method of claim 15 , wherein generating a corrected estimate includes calculating a function of the filtered version of the estimate of the amplitude of the voltage-controlled oscillator, a supply voltage and a pseudo NMOS inverter low voltage level.

17. The method of claim 16 , wherein the pseudo NMOS inverter low voltage level is measured by applying a control signal to a second replica circuit.

18. A method for calibrating a voltage-controlled oscillator with a duty cycle detector, the method comprising:

adjusting a control word coupled to a voltage-controlled oscillator to a maximum value;

applying the output of the voltage-controlled oscillator to a duty cycle detector to generate an estimate of the amplitude of the output of the voltage-controlled oscillator;

periodically sampling the estimate of the amplitude;

calculating a function of a filtered DC voltage, a pseudo NMOS inverter low voltage level, and a supply voltage to generate a modified estimate of the amplitude; and

periodically adjusting the control word as a function of a target value and the modified estimate of the amplitude.

Assignments (10)

Continuity (1)