IP Library Granted Patent US 8,471,720
Granted Patent B2
US 8,471,720 · App. 12/947,890 · Granted Jun 25, 2013

On-chip power supply monitoring using a network of modulators

Inventors: Mark Franklin Turner (Longmont, CO); Jeffrey S. Brown (Fort Collins, CO); Jonathan W. Byrn (Fort Collins, CO)
Assignee: LSI Corporation
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Quick Facts
Patent No.
US 8,471,720
App. No.
12/947,890
Granted
Jun 25, 2013
Kind
B2
Abstract

An apparatus for monitoring at least supply voltage in an IC includes a plurality of monitor circuits distributed throughout the integrated circuit. Each of the monitor circuits is operative to receive the supply voltage, or a signal representative thereof, and to generate an output signal indicative of a comparison between the supply voltage and a reference voltage. The apparatus further includes a control circuit coupled to the plurality of monitor circuits. The control circuit is operative to receive the respective output signals from the plurality of monitor circuits and to generate an output of the apparatus which is a function of information conveyed in the respective output signals from the plurality of monitor circuits.

Claims (71)

1. An apparatus for monitoring at least supply voltage in an integrated circuit, comprising:

a plurality of monitor circuits distributed throughout the integrated circuit, each of the monitor circuits being operative to receive the supply voltage or a signal representative thereof and to generate at least one output signal indicative of a comparison between the supply voltage and a reference voltage; and

a control circuit coupled to the plurality of monitor circuits, the control circuit being operative to receive the respective output signals from the plurality of monitor circuits and to generate an output of the apparatus which is a function of information conveyed in the respective output signals from the plurality of monitor circuits;

wherein at least one of the plurality of monitor circuits comprises:

an integration circuit;

a latching sense amplifier, the latching sense amplifier including a first input connected to the integration circuit, a second input adapted to receive the reference voltage, a control input adapted to receive a control signal supplied to the sense amplifier, and an output for generating the output signal indicative of a comparison between the supply voltage and the reference voltage as a function of the control signal; and

a pull-down circuit coupled to the integration circuit in a feedback configuration, the pull-down circuit being operative to receive the output signal generated by the latching sense amplifier and to provide a current discharge path for controlling a voltage at a common summing node in the integration circuit.

2. The apparatus of claim 1 , wherein the integration circuit comprises:

a pull-up circuit adapted for connection to the supply voltage; and

a capacitive element coupled to the pull-up circuit, the capacitive element being operative to accumulate a voltage for comparison with the reference voltage as a function of at least first and second clock signals supplied to the apparatus.

3. The apparatus of claim 2 , wherein the control signal supplied to the sense amplifier is a logical complement of the first and second clock signals.

4. The apparatus of claim 2 , wherein a duty cycle of at least one of the first and second clock signals is selectively controlled such that the respective pull-up and pull-down circuits have a substantially same effective resistance relative to one another.

5. The apparatus of claim 2 , wherein a strength of the pull-down circuit is adapted to be greater than a strength of the pull-up circuit.

6. The apparatus of claim 1 , wherein the at least one of the plurality of monitor circuits comprises:

a plurality of latching sense amplifiers, each of the latching sense amplifiers including a first input connected to the integration circuit, a second input adapted to receive the reference voltage, a control input adapted to receive a control signal supplied to the sense amplifier, and an output for generating an output signal indicative of a comparison between the supply voltage and the reference voltage as a function of the control signal; and

a plurality of pull-down circuits coupled to the integration circuit in a feedback configuration, each of the respective pull-down circuits being operative to receive the output signal generated by a corresponding one of the latching sense amplifiers and to provide a corresponding current discharge path for controlling a voltage at a common summing node in the integration circuit.

7. The apparatus of claim 6 , wherein the integration circuit comprises:

a pull-up circuit adapted for connection to the supply voltage; and

a capacitive element coupled to the pull-up circuit, the capacitive element being operative to accumulate a voltage for comparison with the reference voltage as a function of at least first and second clock signals supplied to the apparatus.

8. The apparatus of claim 7 , wherein the control signal supplied to the plurality of sense amplifiers is a logical complement of the first and second clock signals.

9. The apparatus of claim 7 , wherein a duty cycle of at least one of the first and second clock signals is selectively controlled such that the respective pull-up and pull-down circuits have a substantially same effective resistance relative to one another.

10. The apparatus of claim 7 , wherein a strength of each of the respective pull-down circuits is adapted to be greater than a strength of the pull-up circuit.

11. The apparatus of claim 1 , wherein each of the plurality of monitor circuits comprises a one-bit delta-sigma modulator.

12. The apparatus of claim 1 , wherein each of the plurality of monitor circuits comprises a multiple-bit delta-sigma modulator.

13. The apparatus of claim 1 , wherein each of the plurality of monitor circuits comprises one of a one-bit delta-sigma modulator and a multiple-bit delta-sigma modulator.

14. The apparatus of claim 1 , wherein the control circuit is further operative to modify at least one operating characteristic of the integrated circuit as a function of the information conveyed in the respective output signals from the plurality of monitor circuits.

15. The apparatus of claim 14 , wherein the at least one operating characteristic of the integrated circuit comprises at least one of the supply voltage, clock frequency, timing and data flow of the integrated circuit.

16. An apparatus for monitoring at least supply voltage in an integrated circuit, comprising:

a plurality of monitor circuits distributed throughout the integrated circuit, each of the monitor circuits being operative to receive the supply voltage or a signal representative thereof and to generate at least one output signal indicative of a comparison between the supply voltage and a reference voltage; and

a control circuit coupled to the plurality of monitor circuits, the control circuit being operative to receive the respective output signals from the plurality of monitor circuits and to generate an output of the apparatus which is a function of information conveyed in the respective output signals from the plurality of monitor circuits;

wherein the control circuit comprises a decimation circuit operative to average at least a subset of the plurality of respective output signals generated by the plurality of monitor circuits to thereby increase a resolution of the output of the apparatus.

17. An apparatus for monitoring at least supply voltage in an integrated circuit, comprising:

a plurality of monitor circuits distributed throughout the integrated circuit, each of the monitor circuits being operative to receive the supply voltage or a signal representative thereof and to generate at least one output signal indicative of a comparison between the supply voltage and a reference voltage; and

a control circuit coupled to the plurality of monitor circuits, the control circuit being operative to receive the respective output signals from the plurality of monitor circuits and to generate an output of the apparatus which is a function of information conveyed in the respective output signals from the plurality of monitor circuits;

wherein the control circuit is further operative to selectively enable or disable at least a subset of the plurality of monitor circuits to thereby form a monitoring network having a programmable resolution.

18. An integrated circuit, comprising:

at least one power supply monitoring network operative to monitor a supply voltage of the integrated circuit, the at least one power supply monitoring network comprising:

a plurality of monitor circuits distributed throughout the integrated circuit, each of the monitor circuits being operative to receive the supply voltage or a signal representative thereof and to generate at least one output signal indicative of a comparison between the supply voltage and a reference voltage; and

a control circuit coupled to the plurality of monitor circuits, the control circuit being operative to receive the respective output signals from the plurality of monitor circuits and to generate an output of the power supply monitoring network which is a function of information conveyed in the respective output signals from the plurality of monitor circuits;

wherein at least one of the plurality of monitor circuits comprises:

an integration circuit;

a latching sense amplifier, the latching sense amplifier including a first input connected to the integration circuit, a second input adapted to receive the reference voltage, a control input adapted to receive a control signal supplied to the sense amplifier, and an output for generating the output signal indicative of a comparison between the supply voltage and the reference voltage as a function of the control signal; and

a pull-down circuit coupled to the integration circuit in a feedback configuration, the pull-down circuit being operative to receive the output signal generated by the latching sense amplifier and to provide a current discharge path for controlling a voltage at a common summing node in the integration circuit.

19. The integrated circuit of claim 18 , wherein the integration circuit comprises:

a pull-up circuit adapted for connection to the supply voltage; and

a capacitive element coupled to the pull-up circuit, the capacitive element being operative to accumulate a voltage for comparison with the reference voltage as a function of at least first and second clock signals supplied to the power supply monitoring network.

20. The integrated circuit of claim 18 , wherein the at least one of the plurality of monitor circuits comprises:

a plurality of latching sense amplifiers, each of the latching sense amplifiers including a first input connected to the integration circuit, a second input adapted to receive the reference voltage, a control input adapted to receive a control signal supplied to the sense amplifier, and an output for generating an output signal indicative of a comparison between the supply voltage and the reference voltage as a function of the control signal; and

a plurality of pull-down circuits coupled to the integration circuit in a feedback configuration, each of the respective pull-down circuits being operative to receive the output signal generated by a corresponding one of the latching sense amplifiers and to provide a corresponding current discharge path for controlling a voltage at a common summing node in the integration circuit.

21. The integrated circuit of claim 20 , wherein the integration circuit comprises:

a pull-up circuit adapted for connection to the supply voltage; and

a capacitive element coupled to the pull-up circuit, the capacitive element being operative to accumulate a voltage for comparison with the reference voltage as a function of at least first and second clock signals supplied to the power supply monitoring network.

22. An electronic system, comprising:

an integrated circuit including at least one power supply monitoring network operative to monitor a supply voltage of the integrated circuit, the at least one power supply monitoring network comprising:

a plurality of monitor circuits distributed throughout the integrated circuit, each of the monitor circuits being operative to receive the supply voltage or a signal representative thereof and to generate at least one output signal indicative of a comparison between the supply voltage and a reference voltage; and

a control circuit coupled to the plurality of monitor circuits, the control circuit being operative to receive the respective output signals from the plurality of monitor circuits and to generate an output of the power supply monitoring network which is a function of information conveyed in the respective output signals from the plurality of monitor circuits;

wherein at least one of the plurality of monitor circuits comprises:

an integration circuit;

a latching sense amplifier, the latching sense amplifier including a first input connected to the integration circuit, a second input adapted to receive the reference voltage, a control input adapted to receive a control signal supplied to the sense amplifier, and an output for generating the output signal indicative of a comparison between the supply voltage and the reference voltage as a function of the control signal; and

a pull-down circuit coupled to the integration circuit in a feedback configuration, the pull-down circuit being operative to receive the output signal generated by the latching sense amplifier and to provide a current discharge path for controlling a voltage at a common summing node in the integration circuit.

23. A method for monitoring at least supply voltage in an integrated circuit including a plurality of monitor circuits distributed throughout the integrated circuit and a control circuit coupled to the plurality of monitor circuits, the method comprising the steps of:

each of the monitor circuits receiving the supply voltage or a signal representative thereof and generating at least one output signal indicative of a comparison between the supply voltage and a reference voltage;

the control circuit receiving the respective output signals from the plurality of monitor circuits and generating an output which is a function of information conveyed in the respective output signals from the plurality of monitor circuits; and

decimating at least a subset of the plurality of respective output signals generated by the plurality of monitor circuits, thereby increasing a resolution of the output of the control circuit.

24. The method of claim 23 , further comprising controlling at least one operating characteristic of the integrated circuit as a function of the information conveyed in the respective output signals from the plurality of monitor circuits.

25. A method for monitoring at least supply voltage in an integrated circuit including a plurality of monitor circuits distributed throughout the integrated circuit and a control circuit coupled to the plurality of monitor circuits, the method comprising the steps of:

each of the monitor circuits receiving the supply voltage or a signal representative thereof and generating at least one output signal indicative of a comparison between the supply voltage and a reference voltage;

the control circuit receiving the respective output signals from the plurality of monitor circuits and generating an output which is a function of information conveyed in the respective output signals from the plurality of monitor circuits;

accumulating a voltage indicative of supply voltage on a capacitive element included in at least one of the plurality of monitor circuits;

comparing the voltage accumulated on the capacitive element with a reference voltage; and

the at least one of the plurality of monitor circuits generating the output signal as a function of a difference between the voltage accumulated on the capacitive element and the reference voltage and on at least first and second clock signals supplied to the at least one of the plurality of monitor circuits.

Assignments (8)
CORRECTIVE ASSIGNMENT TO CORRECT THE EFFECTIVE DATE OF MERGER TO 09/05/2018 PREVIOUSLY RECORDED AT REEL: 047230 FRAME: 0133. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Oct 29, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047630/0456 →
MERGER Recorded Oct 4, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047230/0133 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041710/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032856-0031) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 037684/0039 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 3, 2015
From: LSI CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 035390/0388 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: LSI CORPORATION; AGERE SYSTEMS LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032856/0031 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 17, 2010
From: TURNER, MARK FRANKLIN; BROWN, JEFFREY S; BYRN, JONATHAN W
To: LSI CORPORATION
Reel/Frame 025381/0056 →
Continuity (1)
Related Publication 20120119788A1 · May 17, 2012