Lithography aware timing analysis
A method for performing timing analysis includes receiving information specifying an integrated circuit. A neighborhood of shapes associated with the integrated circuit is then determined. Delay information associated with the integrated circuit is generated based on the neighborhood of shapes. The neighborhood of shapes may be determined by determining a first set of spacings to a boundary of a first cell from an internal shape. A second set of spacings may be determined from the boundary of the first cell to a shape of a second cell. A lithography process may be characterized using the first and second set of spacings.
1. A method for performing delay calculations, the method comprising:
receiving, at one or more computer systems, information specifying an integrated circuit;
determining, with the one or more processors associated with the one or more computer systems, a neighborhood of shapes associated with the integrated circuit, wherein determining the neighborhood of shapes comprises:
determining a first set of spacings between a boundary of an internal shape of a first cell and a boundary of the first cell;
determining a second set of spacings between the boundary of the first cell and a boundary of a shape of a second cell; and
characterizing a lithography process using the first and second set of spacings; and
generating, with the one or more processors associated with the one or more computer systems, delay information associated with the integrated circuit based on calculating delay in the integrated circuit using a simulation of the characterized lithography process.
2. The method of claim 1 wherein characterizing the lithography process comprises characterizing effective transistor channel lengths as a function of the first and second set of spacings.
3. The method of claim 1 further comprising generating a mapping from the first and second set of spacings to the lithography process.
4. The method of claim 1 further comprising generating a mapping from the first and second set of spacings to delay.
5. The method of claim 4 further comprising calculating delay of the first cell based on the first and second set of spacing.
6. The method of claim 1 wherein the internal shape comprises a polysilicon transistor shape.
7. The method of claim 1 wherein the internal shape comprises a wiring shape.
8. A computer program product stored on a non-transitory computer readable medium for performing delay calculations, the computer program product comprising:
code for receiving information specifying an integrated circuit;
code for determining a neighborhood of shapes associated with the integrated circuit, wherein determining the neighborhood of shapes comprises:
determining a first set of spacings between a boundary of an internal shape of a first cell and a boundary of the first cell;
determining a second set of spacings between the boundary of the first cell and a boundary of a shape of a second cell; and
characterizing a lithography process using the first and second set of spacings; and
code for generating delay information associated with the integrated circuit based on calculating delay in the integrated circuit using a simulation of the characterized lithography process.
9. The computer program product of claim 8 wherein the code for characterizing the lithography process comprises code for characterizing effective transistor channel lengths as a function of the first and second set of spacings.
10. The computer program product of claim 8 further comprising code for generating a mapping from the first and second set of spacings to the lithography process.
11. The computer program product of claim 8 further comprising code for generating a mapping from the first and second set of spacings to delay and calculating delay of the first cell based on the first and second set of spacings.
12. The computer program product of claim 9 wherein the internal shape comprises a polysilicon transistor shape.
13. A system for performing delay calculations, the system comprising:
a processor; and
a memory coupled to the processor, the memory configured to store a set of instructions which when executed by the processor cause the processor to:
receive information specifying an integrated circuit;
determine a neighborhood of shapes associated with the integrated circuit based on:
determining a first set of spacings between a boundary of an internal shape of a first cell and a boundary of the first cell;
determining a second set of spacings between the boundary of the first cell and a boundary of a shape of a second cell; and
characterizing a lithography process using the first and second set of spacings; and
generate delay information associated with the integrated circuit based on calculating delay in the integrated circuit using a simulation of the characterized lithography process.
14. The system of claim 13 wherein the processor is caused to characterize effective transistor channel lengths as a function of the first and second set of spacings to characterize the lithography process.
15. The system of claim 13 wherein the processor is further caused to generate a mapping from the first and second set of spacings to the lithography process.
16. The system of claim 13 wherein the processor is further caused to generate a mapping from the first and second set of spacings to delay and calculate delay of the first cell based on the first and second set of spacings.
17. The system of claim 13 wherein the internal shape comprises a polysilicon transistor shape.