Fabrication technique for high frequency, high power group III nitride electronic devices
Fabrication methods of a high frequency (sub-micron gate length) operation of AlInGaN/InGaN/GaN MOS-DHFET, and the HFET device resulting from the fabrication methods, are generally disclosed. The method of forming the HFET device generally includes a novel double-recess etching and a pulsed deposition of an ultra-thin, high-quality silicon dioxide layer as the active gate-insulator. The methods of the present invention can be utilized to form any suitable field effect transistor (FET), and are particular suited for forming high electron mobility transistors (HEMT).
1. A method of forming a high electron mobility transistor (HEMT) device, the method comprising:
providing a HEMT structure comprising a substrate, a buffer layer over the substrate, a spacer layer over the buffer layer, and a group III nitride epilayer over the spacer layer;
positioning a source metal electrode and a drain metal electrode on the group III nitride epilayer;
etching a first recess in the group III nitride epilayer;
after formation of the first recess in the group III nitride epilayer, fluorine isolation etching in the first recess;
thereafter, etching a second recess in the group III nitride epilayer, wherein the second recess is positioned within the first recess;
thereafter, depositing a dielectric layer in the second recess; and
thereafter, positioning a gate electrode on the dielectric layer deposited in the second recess.
2. The method as in claim 1 , wherein the dielectric layer is deposited via a digital dielectric deposition method comprising:
pulsing a silicon source and an oxygen source to deposit the dielectric layer in the second recess.
3. The method as in claim 1 , wherein the fluorine isolation etching is achieved with sulphur hexafluoride gas and carbon tertafluoride gas.
4. The method as in claim 1 , wherein the second recess etching is followed by a soft anneal at anneal temperature range of 60° C. to about 420° C. for a time period ranging from about 30 seconds to about 120 minutes.
5. The method as in claim 1 , further comprising:
growing a silicon based passivation layer around the gate electrode, wherein the silicon based passivation layer is deposited via a digital dielectric deposition method; and
positioning a field plate electrode on the silicon based passivation layer.
6. The method as in claim 1 , wherein the buffer layer includes a plurality of layers.
7. The method as in claim 1 , wherein the group III nitride epilayer comprises Al x In y Ga 1-x-y N, wherein 0≦x≦1, 0≦y≦1 and 0<x+y≦1.
8. The method as in claim 7 , wherein the group III nitride epilayer comprises a short period super lattice, wherein the short period super lattice is grown via pulsed atomic layer epitaxy to form adjacent layers having a chemical structure of Al x In y Ga 1-x-y N and Al r In s Ga (1-r-s) N, respectfully, wherein 0≦x≦1, 0≦y≦1, 0<x+y≦1, 0≦r≦1, 0≦s≦1, 0<r+s≦1, and wherein x and r are different and y and s are different.
9. The method as in claim 1 , wherein the spacer layer is deposited by pulsed atomic layer epitaxy and comprises Al x In y Ga 1-x-y N, wherein 0≦x≦1, 0≦y≦1 and 0<x+y≦1.
10. The method as in claim 1 , wherein the dielectric layer comprises silicon oxide or silicon nitride.
11. The method as in claim 10 , wherein the dielectric layer is deposited in the second recess and directly on the group III nitride epilayer.
12. The method as in claim 11 , wherein the dielectric layer comprises a silicon oxide material having the structure Si x O y , where x is an integer that is from 1 to 5 and y is a number from about 0.5 to about 6.
13. The method as in claim 12 , wherein y is from about 1 to about 5.
14. The method as in claim 12 , wherein the dielectric layer comprises silicon dioxide.
15. The method as in claim 11 , wherein the dielectric layer comprises a silicon nitride material having the formula Si u N v , where 1≦u≦5 and 2≦v≦8.
16. The method as in claim 15 , wherein the dielectric layer comprises silicon nitride.