IP Library Granted Patent US 8,477,224
Granted Patent B2
US 8,477,224 · App. 12/692,848 · Granted Jul 2, 2013

Solid-state imaging apparatus

Inventors: Masanori Ogura (Kawasaki, JP); Toru Koizumi (Yokohama, JP)
Assignee: Canon Kabushiki Kaisha
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Quick Facts
Patent No.
US 8,477,224
App. No.
12/692,848
Granted
Jul 2, 2013
Kind
B2
Abstract

Provided is a solid-state imaging apparatus that is capable of preventing a harmful influence due to noise generated in a control line. The solid-state imaging apparatus includes: a plurality of pixels each including a photoelectric conversion unit for photoelectric converting to generate a signal; control lines for supplying control signals for driving the pixels; driving buffers for driving the control lines; and switching units for switching between a first path for supplying power source voltages from power source circuits to power source terminals of the driving buffers and a second path for supplying power source voltages from capacitors to the power source terminals of the driving buffers.

Claims (40)

1. A solid-state imaging apparatus comprising:

a plurality of pixels each including a photoelectric conversion unit to generate a signal;

a control line configured to supply a control signal for driving the pixels;

a driving buffer configured to drive the control line; and

a switching unit configured to switch between a first path for supplying a power source voltage from a power source circuit to a power source terminal of the driving buffer and a second path for supplying a power source voltage from a capacitor to the power source terminal of the driving buffer,

wherein the switching unit selects the second path during a pixel signal reading out period in which a signal is read out from one of the pixels to outside of the one of the pixels.

2. The solid-state imaging apparatus according to claim 1 , wherein

the switching unit selects the first path during a period except for the pixel signal reading out period.

3. The solid-state imaging apparatus according to claim 1 , further comprising:

a vertical output line configured to output the signals from the pixels; and

a column amplifier configured to amplify the signals from the vertical output line,

wherein the switching unit selects the second path pixel during the signal reading out period, when the column amplifier amplifies the signal with a gain larger than 1.

4. The solid-state imaging apparatus according to claim 1 ,

wherein each pixel includes:

a transfer switch configured to transfer the signal generated by the photoelectric conversion unit;

a reset switch configured to reset of the signal in the photoelectric conversion unit;

a pixel amplifier configured to amplify the signal transferred by the transfer switch; and

a selecting switch configured to select a signal output from the pixel amplifier, and

wherein the control line controls the transfer switch, the reset switch, and the selecting switch.

5. The solid-state imaging apparatus according to claim 4 , wherein

the transfer switch, the reset switch, and the selecting switch are MOS transistors, and

the control line is electrically connected to gate electrodes of the transfer switch, the reset switch and the selecting switch.

6. The solid-state imaging apparatus according to claim 1 ,

wherein each pixel includes

a transfer switch configured to transfer the signal generated by the photoelectric conversion unit;

a reset switch configured to reset of the signal in the photoelectric conversion unit; and

a pixel amplifier configured to amplify the signal transferred by the transfer switch, and

wherein the control line controls the transfer switch, the reset switch, and reset potentials of the reset switch.

7. The solid-state imaging apparatus according to claim 1 , wherein

the capacitor has a power source voltage holding electrode and an electrode being at the same voltage as a reference voltage of one of the pixels and arranged in opposition to the power source voltage holding electrode.

8. The solid-state imaging apparatus comprising:

a plurality of pixel each including a photoelectric conversion unit to generate a signal;

a control line configured to supply a control signal for driving the pixels;

a driving buffer configured to drive the control line; and

a switching unit configured to switch between a first path for supplying a power source voltage from a power source circuit to a power source terminal of the driving buffer and a second path for supplying a power source voltage from a capacitor to the power source terminal of the driving buffer,

wherein each of the pixels includes:

a transfer switch configured to transfer the signal generated by the photoelectric conversion unit; and

a reset switch configured to reset the signal in the photoelectric conversion unit,

wherein the control line controls the transfer switch and the reset switch, and

wherein the switching unit selects the first path at least during a period of controlling the reset switch, and a period controlling the transfer switch.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 16, 2010
From: OGURA, MASANORI; KOIZUMI, TORU
To: CANON KABUSHIKI KAISHA
Reel/Frame 024241/0622 →
Priority Claims (1)
JP 2009-020135 · Jan 30, 2009 · national
Continuity (1)
Related Publication 20100194947A1 · Aug 5, 2010