Phase change memory and method for fabricating the same
View Patent ↗The invention provides a phase change memory and a method for forming the phase change memory. The phase change memory includes a storage region and a peripheral circuit region. The peripheral circuit region has a peripheral substrate, a plurality of peripheral shallow trench isolation (STI) units in the peripheral substrate, and at least one MOS transistor on the peripheral substrate and between the peripheral STI units. The storage region has a storage substrate, an N-type ion buried layer on the storage substrate, a plurality of vertical LEDs on the N-type ion buried layer, a plurality of storage shallow trench isolation (STI) units between the vertical LEDs, and a plurality of phase change layers on the vertical LED and between the storage STI units. The storage STI units have thickness substantially equal to thickness of the vertical LEDs. The peripheral STI units have thickness substantially equal to thickness of the storage STI units. The N-type conductive region contains SiC. A top of P-type conductive region is flush with a top of the peripheral substrate. The N-type conductive region containing SiC reduces drain current through the vertical LED and raises current efficiency of the vertical LED. The peripheral circuit region can work normally without adverse influence on performance of the phase change memory.
1. A method for fabricating a phase change memory, comprising:
providing a substrate including a storage substrate and a peripheral substrate;
forming a sacrificial dielectric layer on the peripheral substrate;
etching the storage substrate and forming an N-type ion buried layer on the storage substrate;
forming a plurality of vertical LEDs on the N-type ion buried layer, each vertical LED comprising an N-type conductive region containing SiC on the N-type ion buried layer, and a P-type conductive region on the N-type conductive region, a top of P-type conductive region being flush with a top of the peripheral substrate;
removing the sacrificial dielectric layer on the peripheral substrate;
forming a plurality of storage STI units between the vertical LEDs, and forming a plurality of peripheral STI units in the peripheral substrate, the storage STI units having thickness substantially equal to thickness of the vertical LEDs, and the peripheral STI units having thickness substantially equal to thickness of the storage STI units; and
forming a plurality of phase change layers on the vertical LEDs and between the storage STI units, and forming at least one MOS transistor on the peripheral substrate and between the peripheral STI units.
2. The method according to claim 1 , wherein the N-type ion buried layer is formed by implanting N-types ions into the storage substrate before etching the storage substrate.
3. The method according to claim 1 , wherein the N-type ion buried layer is formed by implanting N-types ions into the storage substrate after etching the storage substrate.
4. The method according to claim 1 , wherein the N-type conductive region is formed on the N-type ion buried layer by selective epitaxial growth, and reaction gases for selective epitaxial growth comprise SiC and N-type ions.
5. The method according to claim 4 , wherein the reaction gas SiC has C concentration with a molar ratio ranging from 1% to 3%.
6. The method according to claim 4 , wherein a SiC layer is formed on the N-type ion buried layer by selective epitaxial growth, and N-type ions are implanted into the SiC layer for forming the N-type conductive region.
7. The method according to claim 6 , wherein the reaction gas SiC has C concentration with a molar ratio ranging from 1% to 3%.
8. The method according to claim 1 , wherein the P-type conductive region is formed on the N-type conductive region by selective epitaxial growth, and wherein reaction gases comprise SiGe and P-type ions.
9. The method according to claim 8 , wherein a SiGe layer is formed on the N-type conductive region by selective epitaxial growth, and P-type ions are implanted into the SiGe layer for forming the P-type conductive region.
10. The method according to claim 1 , wherein the sacrificial dielectric layer has thickness ranging from 5 nm to 50 nm.
11. The method according to claim 1 , wherein oxide or nitride is deposited on the peripheral substrate by low pressure chemical vapor deposition for forming the sacrificial dielectric layer.
12. The method according to claim 1 , wherein oxide or nitride is deposited on the peripheral substrate by plasma enhanced chemical vapor deposition for forming the sacrificial dielectric layer.