Method and apparatus for the erase suspend operation
Various aspects of a nonvolatile memory have an improved erase suspend procedure. A bias arrangement is applied to word lines of an erase sector undergoing an erase procedure interrupted by an erase suspend procedure. As a result, another operation performed during erase suspend, such as a read operation or program operation, has more accurate results due to decreased leakage current from any over-erased nonvolatile memory cells of the erase sector.
1. An apparatus, comprising:
a memory array of an integrated circuit, including a plurality of erase sectors of nonvolatile memory cells;
a plurality of word lines accessing the nonvolatile memory cells; and
control logic of the integrated circuit,
wherein the control logic is responsive to an erase command by performing a multi-phase erase procedure on an erase sector of the plurality of erase sectors of the memory array, and
wherein the control logic is responsive to an erase suspend command by performing an erase suspend procedure suspending the multi-phase erase procedure and allowing a non-erase command to perform a non-erase procedure on the memory array, and the erase suspend procedure applies a bias arrangement to at least one of the plurality of word lines accessing the erase sector during the non-erase procedure, the bias arrangement decreasing leakage from over-erased nonvolatile memory cells of the erase sector.
2. The apparatus of claim 1 , wherein the erase suspend procedure applies the bias arrangement, responsive to the erase suspend procedure suspending the multi-phase erase procedure when the multi-phase erase procedure is in an erase phase.
3. The apparatus of claim 1 , wherein the erase suspend procedure applies the bias arrangement, responsive to the erase suspend procedure suspending the multi-phase erase procedure when the multi-phase erase procedure is in a soft program phase after an erase phase.
4. The apparatus of claim 1 , wherein the erase suspend procedure does not apply the bias arrangement, responsive to the erase suspend procedure suspending the multi-phase erase procedure when the multi-phase erase procedure is in a pre-program phase before an erase phase.
5. The apparatus of claim 1 , wherein the erase suspend procedure does not apply the bias arrangement, responsive to the erase suspend procedure suspending the multi-phase erase procedure when the multi-phase erase procedure is in a verify phase.
6. The apparatus of claim 1 , wherein the non-erase command is a read command and the non-erase procedure is a read procedure.
7. The apparatus of claim 1 , wherein the non-erase command is a program command and the non-erase procedure is a program procedure.
8. The apparatus of claim 1 , wherein the non-erase command is a program command and the non-erase procedure is a program procedure including a program verify phase, and the erase suspend procedure applies the bias arrangement during the program verify phase.
9. The apparatus of claim 1 , wherein the non-erase procedure is performed on a selected memory cell sharing a same well with at least one of the over-erased nonvolatile memory cells of the erase sector.
10. The apparatus of claim 1 , wherein the non-erase procedure is performed on a selected memory cell sharing a same bit line with at least one of the over-erased nonvolatile memory cells of the erase sector.
11. A method, comprising:
performing an erase suspend procedure on a memory array of the integrated circuit, by suspending a multi-phase erase procedure of an erase sector of the memory array;
performing a non-erase procedure on the memory array; and
applying a bias arrangement to at least one word line accessing the erase sector during the non-erase procedure, the bias arrangement decreasing leakage from over-erased nonvolatile memory cells of the erase sector.
12. The method of claim 11 , wherein the erase suspend procedure applies the bias arrangement, responsive to the erase suspend procedure suspending the multi-phase erase procedure when the multi-phase erase procedure is in an erase phase.
13. The method of claim 11 , wherein the erase suspend procedure applies the bias arrangement, responsive to the erase suspend procedure suspending the multi-phase erase procedure when the multi-phase erase procedure is in a soft program phase after an erase phase.
14. The method of claim 11 , wherein the erase suspend procedure does not apply the bias arrangement, responsive to the erase suspend procedure suspending the multi-phase erase procedure when the multi-phase erase procedure is in a pre-program phase before an erase phase.
15. The method of claim 11 , wherein the erase suspend procedure does not apply the bias arrangement, responsive to the erase suspend procedure suspending the multi-phase erase procedure when the multi-phase erase procedure is in a verify phase.
16. The method of claim 11 , wherein the non-erase command is a read command and the non-erase procedure is a read procedure.
17. The method of claim 11 , wherein the non-erase command is a program command and the non-erase procedure is a program procedure.
18. The method of claim 11 , wherein the non-erase command is a program command and the non-erase procedure is a program procedure including a program verify phase, and the erase suspend procedure applies the bias arrangement during the program verify phase.
19. The method of claim 11 , wherein the non-erase procedure is performed on a selected memory cell sharing a same well with at least one of the over-erased nonvolatile memory cells of the erase sector.
20. The method of claim 11 , wherein the non-erase procedure is performed on a selected memory cell sharing a same bit line with at least one of the over-erased nonvolatile memory cells of the erase sector.