Semiconductor device including fuse array and method of operation the same

1. A semiconductor device comprising:

a fuse array that comprises a first portion of fuses and a second portion of fuses;

a first group of sense amplifier circuits that senses information stored in the first portion of fuses in the fuse array and outputs a first group of fuse data;

a second group of sense amplifier circuits that senses information stored in the second portion of fuses in the fuse array and outputs a second group of fuse data;

a first register unit including a first group of registers that receives and transfers the first group of fuse data in response to a first transfer clock and a second group of registers that receives and transfers the second group of fuse data in response to a second transfer clock;

a multiplexer that selectively outputs the first and second group of fuse data; and

a second register unit that receives the fuse data from the multiplexer in response to a third transfer clock.

2. The semiconductor device of claim 1 , wherein the fuse array comprises m rows and n columns, wherein the first register unit comprises a*n registers and stores fuse data of a rows of the fuse array (m, n, and a are each an integer equal to or greater than 1), and wherein fuse data stored in one row of the a rows is output in parallel to the first register unit.

3. The semiconductor device of claim 2 , wherein the second register unit comprises m*n registers and stores the fuse data of the m rows of the fuse array.

4. The semiconductor device of claim 1 , wherein the fuse array includes antifuses, and each antifuse comprises one fuse transistor connected to a high voltage and one select transistor connected to a word line and a bit line, and wherein it is determined whether each of the antifuses is programmed according to voltage levels of at least one of the high voltage, the word line, and the bit line.

5. The semiconductor device of claim 1 , wherein the semiconductor device further comprises a cell region in which a memory cell array is disposed and a peri region in which one or more peripheral circuits are positioned, and wherein the fuse array is positioned at the peri region and at least one register of the second register unit is positioned at the cell region.

6. The semiconductor device of claim 1 , wherein when the semiconductor device is initially driven, a read operation of the fuse array is initiated by sensing whether a level of an internal voltage reaches a threshold value.

7. The semiconductor device of claim 1 , wherein the fuse array comprises a plurality of rows and columns, and wherein the semiconductor device further comprises an address generating unit that generates a row address for driving rows of the fuse array, wherein one or more rows of the fuse array is masked to disable a corresponding row address.

8. The semiconductor device of claim 1 , further comprising a masking circuit that is disposed to correspond to one or more registers of the second register unit, wherein the fuse data is prevented from being provided to the one or more registers while the masking circuits are enabled.

9. A method of operating a semiconductor device comprising a fuse array, wherein the fuse array comprises a first portion of fuses and a second portion of fuses, the method comprising:

sensing, in a first group of sense amplifier circuits, information stored in the first portion of fuses in the fuse array for outputting a first group of fuse data;

sensing, in a second group of sense amplifier circuits, information stored in the second portion of fuses in the fuse array for outputting a second group of fuse data;

storing the first group of fuse data in a first group of registers of a first register unit;

transmitting the first group of fuse data stored in the first group of registers in response to a first transfer clock to a multiplexer and the second group of fuse data stored in the second group of registers to a second transfer clock to the multiplexer;

selectively outputting, by the multiplexer, the first and second group of fuse data to a second register unit; and

setting an operating environment of the semiconductor device by processing the fuse data stored in the second register unit.

10. The method of claim 9 , further comprising:

supplying power to the semiconductor device; and

detecting a level of an internal voltage of the semiconductor device, wherein when the level of the internal voltage reaches a threshold value, the reading of the information is initiated.

11. The method of claim 9 , wherein the fuse array comprises m rows and n columns, wherein the first register unit comprises a*n registers and stores fuse data of a rows of the fuse array, and wherein the second register unit comprises m*n registers and stores fuse data of the rows of the fuse array (where m, n, and a are each an integer equal to or greater than 1).

12. The method of claim 9 , wherein the fuse array comprises a plurality of rows and columns, and further comprising generating a plurality of row addresses in order to drive the rows of the fuse array, wherein at least some of the plurality of row addresses are disabled in response to preset masking information.

13. The method of claim 9 , wherein the fuse array comprises a plurality of antifuses positioned in an array.