IP Library Granted Patent US 8,492,756
Granted Patent B2
US 8,492,756 · App. 12/683,695 · Granted Jul 23, 2013

Semiconductor device and method for manufacturing the same

Inventors: Junichiro Sakata (Atsugi, JP); Takashi Shimazu (Machida, JP); Hiroki Ohara (Sagamihara, JP); Toshinari Sasaki (Atsugi, JP); Shunpei Yamazaki (Setagaya, JP)
Assignee: Semiconductor Energy Laboratory Co., Ltd.
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Quick Facts
Patent No.
US 8,492,756
App. No.
12/683,695
Granted
Jul 23, 2013
Kind
B2
Abstract

An object is to provide a semiconductor device including a thin film transistor which includes an oxide semiconductor layer and has high electric characteristics. An oxide semiconductor layer including SiO x is used in a channel formation region, and in order to reduce contact resistance with source and drain electrode layers formed using a metal material with low electric resistance, source and drain regions are provided between the source and drain electrode layers and the oxide semiconductor layer including SiO x . The source and drain regions are formed using an oxide semiconductor layer which does not include SiO x or an oxynitride film.

Claims (57)

1. A method for manufacturing a semiconductor device comprising the steps of:

forming a gate electrode over an insulating surface;

forming an insulating layer over the gate electrode;

forming an oxide semiconductor layer including SiO x over the insulating layer by a sputtering method with use of a first oxide semiconductor target containing SiO 2 at from 0.1 wt % to 20 wt % inclusive; and

forming an oxynitride layer over the oxide semiconductor layer including SiO x by a sputtering method with use of a second oxide semiconductor target in an atmosphere containing nitrogen.

2. The method for manufacturing a semiconductor device according to claim 1 , further comprising the steps of, after forming the oxynitride layer, removing a part of the oxynitride layer which overlaps with the gate electrode, so that the oxide semiconductor layer including SiO x is partly exposed.

3. The method for manufacturing a semiconductor device according to claim 1 , wherein the oxide semiconductor layer including SiO x comprises an In—Ga—Zn-based oxide semiconductor.

4. A method for manufacturing a semiconductor device comprising the steps of:

forming an oxide semiconductor layer including SiO x over an insulating surface by a sputtering method with use of a first oxide semiconductor target containing SiO 2 at from 0.1 wt % to 20 wt % inclusive;

forming an oxynitride layer over the oxide semiconductor layer including SiO x by a sputtering method with use of a second oxide semiconductor target in an atmosphere containing nitrogen;

forming an insulating layer covering the oxynitride layer; and

forming a gate electrode over the insulating layer.

5. The method for manufacturing a semiconductor device according to claim 4 , wherein the oxide semiconductor layer including SiO x comprises an In—Ga—Zn-based oxide semiconductor.

6. A semiconductor device comprising:

a gate electrode over an insulating surface;

an oxide semiconductor layer including SiO x over the insulating surface;

an insulating layer between the gate electrode and the oxide semiconductor layer including SiO x ;

a source electrode layer;

a drain electrode layer; and

a source region interposed between the oxide semiconductor layer including SiO x and the source electrode layer;

a drain region interposed between the oxide semiconductor layer including SiO x and the source and drain electrode layer,

wherein each of the source region and the drain region comprises an oxynitride material.

7. The semiconductor device according to claim 6 , wherein the oxide semiconductor layer including SiO x includes tin.

8. The semiconductor device according to claim 6 , wherein the oxide semiconductor layer including SiO x includes zinc.

9. The semiconductor device according to claim 6 , wherein the oxide semiconductor layer including SiO x is formed by a sputtering method with use of an oxide semiconductor target containing SiO 2 at from 0.1 wt % to 20 wt % inclusive.

10. The semiconductor device according to claim 6 , wherein the oxide semiconductor layer including SiO x comprises a channel region that overlaps with the gate electrode.

11. The semiconductor device according to claim 6 , wherein a whole of the oxide semiconductor layer including SiO x overlaps with the gate electrode.

12. The semiconductor device according to claim 6 , wherein the oxide semiconductor layer including SiO x comprises an In—Ga—Zn-based oxide semiconductor.

13. The semiconductor device according to claim 6 , wherein the oxide semiconductor layer including SiO x comprises indium.

14. The semiconductor device according to claim 6 , wherein each of the source electrode layer and the drain electrode layer comprises titanium.

15. The semiconductor device according to claim 1 , wherein each of the source electrode layer and the drain electrode layer comprises one of tungsten and tantalum.

16. The semiconductor device according to claim 1 , wherein the gate electrode is provided under the oxide semiconductor layer including SiO x .

17. The semiconductor device according to claim 1 ,

wherein the oxide semiconductor layer including SiO x comprises a portion, and

wherein the portion is an amorphous state.

18. A semiconductor device comprising:

a gate electrode;

an oxide semiconductor layer adjacent to the gate electrode;

an insulating layer between the gate electrode and the oxide semiconductor layer;

a source electrode layer;

a drain electrode layer; and

a source region interposed between the oxide semiconductor layer and the source electrode layer; and

a drain region interposed between the oxide semiconductor layer and the drain electrode layer,

wherein each of the source region and the drain region comprises an oxynitride material,

wherein the oxide semiconductor layer comprises a portion, and

wherein a concentration of silicon in the portion is larger than a concentration of silicon in the source region and the drain region.

19. The semiconductor device according to claim 18 , wherein the portion is an amorphous state.

20. The semiconductor device according to claim 18 , wherein the oxide semiconductor layer includes tin.

21. The semiconductor device according to claim 18 , wherein the oxide semiconductor layer includes zinc.

22. The semiconductor device according to claim 18 , wherein the oxide semiconductor layer comprises indium.

23. The semiconductor device according to claim 18 , wherein the oxide semiconductor layer is formed by a sputtering method with use of an oxide semiconductor target containing SiO 2 at from 0.1 wt % to 20 wt % inclusive.

24. The semiconductor device according to claim 18 , wherein the oxide semiconductor layer comprises a channel region that overlaps with the gate electrode.

25. The semiconductor device according to claim 18 , wherein a whole of the oxide semiconductor layer overlaps with the gate electrode.

26. The semiconductor device according to claim 18 , wherein the oxide semiconductor layer comprises an In—Ga—Zn-based oxide semiconductor.

27. The semiconductor device according to claim 18 , wherein each of the source electrode layer and the drain electrode layer comprises titanium.

28. The semiconductor device according to claim 18 , wherein each of the source electrode layer and the drain electrode layer comprises one of tungsten and tantalum.

29. The semiconductor device according to claim 18 , wherein the gate electrode is provided under the oxide semiconductor layer.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 7, 2010
From: SAKATA, JUNICHIRO; SHIMAZU, TAKASHI; OHARA, HIROKI; SASAKI, TOSHINARI; YAMAZAKI, SHUNPEI
To: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Reel/Frame 023747/0484 →
Priority Claims (1)
JP 2009-013532 · Jan 23, 2009 · national
Continuity (1)
Related Publication 20100187523A1 · Jul 29, 2010