Multi-phase DC-to-DC converter with daisy chained pulse width modulation generators
A multi-phase DC-DC converter is disclosed. The DC-DC converter has a plurality of phases, each with a separate PWM generator for driving a totem pole of transistors. A master PWM generator operates off of a master clock signal. The remainder of the phases are slaved to the master PWM generator.
1. A circuit comprising:
a first node having an analog supply voltage;
a second node having a high-side voltage;
a third node having a low-side voltage;
a functional unit to sample a master clock signal having a sequence of pulses based on a phase of the master clock signal to provide an internal clock signal, wherein the phase is determined by the ratio of numerator and a denominator, wherein the numerator is the difference between the analog supply voltage and the high-side voltage, and the denominator is the difference between the high-side voltage and the low-side voltage;
a pulse width modulation generator to provide a pulse width modulation signal clocked by the internal clock signal; and
a high-side power transistor and a low-side power transistor coupled to the pulse width modulation generator to switch on and off in response to the pulse width modulation signal, so that the high-side power transistor is on only if the pulse width modulation signal is in a first logical state, and the low-side power transistor is on only if the pulse width modulation signal is in a second logical state complementary to the first logical state, such that both the high-side and low-side power transistors are not simultaneously on.
2. The circuit as set forth in claim 1 , further comprising:
a master clock signal input port to receive the master clock signal.
3. The circuit as set forth in claim 1 , further comprising:
a clock generator to provide the master clock signal.
4. The circuit as set forth in claim 1 , wherein the high-side voltage is equal to the analog supply voltage.
5. The circuit as set forth in claim 1 , further comprising:
a resistor having a first terminal connected to the second node, and having a second terminal connected to the third node.
6. A system comprising a set of dice {D(i), i=0, 1, 2, . . . , N}, where N is an integer greater than 0,
the die D(0) comprising a clock generator to provide a master clock signal, and the die D(i) coupled to the clock generator to receive the master clock signal for each i=1, 2, . . . , N;
the die D(i) comprising a node n1( i ) having an analog supply voltage, a node n2( i ) having a voltage, and a node n3( i ) having a voltage, for each i=0, 1, 2, . . . , N; wherein the voltage of the node n2(0) is the analog supply voltage, and the voltage of the node n3(N) is at a ground potential; wherein the node n3( i ) is connected to the node n2( i+ 1) for each i=0, 1, . . . , N−1; and
the die D(i) to sample the master clock signal based on a phase P(i) of the master clock signal to provide an internal clock signal c(i), wherein the phase P(i) is determined by the ratio of a numerator and a denominator, wherein the numerator is the difference between the analog supply voltage and the voltage of the node n2( i ), and the denominator is the difference between the voltage of the node n2( i ) and the voltage of the node n3( i ) for each i=0, 1, . . . , N.
7. The system as set forth in claim 6 , wherein the die D(i) comprises a resistor R(i) having a first terminal connected to the node n2( i ) and a second terminal connected to the node n3( i ) for each i=0, 1, . . . , N.
8. The system as set forth in claim 6 , wherein
the die D(i) comprises a pulse width modulation generator G(i) to provide a pulse width modulation signal PWM(i) clocked by the internal clock signal for each i=1, 2, . . . , N; and
the die D(i) comprises a high-side power transistor TH(i) and a low-side power transistor TL(i) coupled to the pulse width modulation generator G(i) to switch on and off in response to the pulse width modulation signal PWM(i), so that the high-side power transistor TH(i) is on only if the pulse width modulation signal PWM(i) is in a first logical state, and the low-side power transistor TL(i) is on only if the pulse width modulation signal PWM(i) is in a second logical state complementary to the first logical state, such that both the high-side power transistor TH(i) and low-side power transistor TL(i) are not simultaneously on, for each i=1, 2, . . . , N.
9. The system as set forth in claim 8 , further comprising:
a set of inductors {L(i), i=0, 1, 2, . . . , N}, where the TL(i) is coupled to the high-side power transistor TH(i) and to the low-side transistor TL(i) for each i=1, 2, . . . , N.