Output driver circuit
Disclosed is an output driver circuit capable of realizing reduction in power consumption, and/or enhancement in transmission waveform quality in addition to an increase in transmission speed. The output driver circuit is provided with, for example, a voltage-signal generation circuit block VSG_BK for driving positive negative output-nodes (TXP, TXN) by voltage, -pulse-signal generation circuits PGEN 1 , PGEN 2 for generating a pulse signal upon a transition of data input signals DIN_P, DIN_N, and current-signal generation circuit blocks ISG_BKp 1 , ISG_BKn 1 , for driving TXP, TXN by current for the duration of a pulse width of the pulse-signal. The current-signal generation circuit block executes high-speed charging of parasitic capacitors Cp 1 , Cp 2 , occurring to TXP, TXN, respectively, while executing charging of parasitic capacitors Cp 1 , Cp 2 , occurring to impedance Z 0 respectively. VSG_BK decides a voltage level at TXP, TXN, in the stationary state, keeping TXP, TXN as terminal nodes at impedance Z 0 , respectively.
1. An output driver circuit comprising:
a first circuit that controls ON/OFF between a positive differential output node and a first power source;
a second circuit that controls ON/OFF between a negative differential output node and a second power source lower in voltage than the first power source;
a third circuit that controls ON/OFF between the negative differential output node and the first power source;
a fourth circuit that controls ON/OFF between the positive differential output node and the second power source;
a first pulse generation circuit that generates a first pulse-signal at a time when a differential input node has made a transition from a first logical level to a second logical level;
a second pulse generation circuit that generates a second pulse-signal at a time when the differential input node has made a transition from the second logical level to the first logical level;
a first current circuit that causes a charging current to flow to the positive differential output node;
a second current circuit that causes a discharging current to flow to the negative differential output node;
a third current circuit that causes a charging current to flow to the negative differential output node;
a fourth current circuit that causes a discharging current to flow to the positive differential output node,
wherein the first circuit and the second circuit each are controlled so as to be in the ON state and to have a first impedance at a time when the differential input node is at the second logical level while the first circuit and the second circuit each are controlled so as to be in the OFF state at a time when the differential input node is at the first logical level,
wherein the third circuit and the fourth circuit each are controlled so as to be in the ON state and to have the first impedance at the time when the differential input node is at the first logical level while the third circuit and the fourth circuit each are controlled so as to be in the OFF state at the time when the differential input node is at the second logical level,
wherein the first current circuit and the second current circuit each cause current to flow for a period of a pulse width of the first pulse-signal,
wherein the third current circuit and the fourth current circuit each cause current to flow for a period of a pulse width of the second pulse-signal, and
wherein the pulse width of the first pulse-signal and the pulse width of the second pulse-signal are each controlled so as to be variable according to setting.
2. The output driver circuit according to claim 1 ,
wherein the first pulse-signal includes third and fourth pulse-signals,
wherein the second pulse-signal includes fifth and sixth signals,
wherein the first current circuit causes the charging current to flow for a period of a pulse width of the third pulse-signal,
wherein the second current circuit causes the discharging current to flow for a period of a pulse width of the fourth pulse-signal,
wherein the third current circuit causes the charging current to flow for period of a pulse width of the fifth pulse-signal,
wherein the fourth current circuit causes the discharging current to flow for period of a pulse width of the sixth pulse-signal,
wherein the pulse width of the third pulse-signal is decided according to a set delay amount of a first variable delay circuit,
wherein the pulse width of the fourth pulse-signal is decided according to a set delay amount of a second variable delay circuit,
wherein the pulse width of the fifth pulse-signal is decided according to a set delay amount of a third variable delay circuit, and
wherein the pulse width of the sixth pulse-signal is decided according to a set delay amount of a fourth variable delay circuit.