Electrostatic discharge circuit for radio frequency transmitters

1. A radio frequency (RF) transmitter comprising:

a power amplifier having an input that is configured to receive RF signals and an output that is configured to transmit the amplified RF signals to an antenna; and

an electrostatic discharge (ESD) protection circuit that is electrically coupled to the output of the power amplifier, wherein the ESD protection circuit includes

a silicon-controlled rectifier (SCR) that is electrically coupled to the output of the power amplifier,

an ESD detection circuit that is configured to trigger the SCR responsive to detecting an electrostatic discharge on an ESD bus,

an ESD clamp circuit that is coupled to the first voltage line;

at least one ESD component electrically coupled between the ESD bus and the first voltage line; and

at least one ESD component coupled between the SCR and a second voltage line having a lower voltage value than the first voltage line.

2. The RF transmitter of claim 1 , wherein the SCR comprises:

an alternating arrangement of a first N-type semiconductor material, a first P-type semiconductor material, a second P-type semiconductor material, a second N-type semiconductor material and a third P-type semiconductor material, wherein shallow trench isolations (STIs) are located at the ends of the alternating arrangement and between the first P-type semiconductor material and the second P-type semiconductor material, wherein the output of the power amplifier, the ESD detection circuit, and a second voltage line are electrically coupled to the first P-type semiconductor material, the second P-type semiconductor material, and the second N-type and third P-type semiconductor material, respectively.

3. The RF transmitter of claim 1 , wherein the first P-type and first N-type semiconductor materials are implanted in an N-well and the second P-type, second N-type and third P-type semiconductor materials are implanted in a P-well, wherein both the N-well and the P-well are formed in a P substrate.

4. The RF transmitter of claim 2 , wherein the ESD bus is coupled between the SCR and the ESD detection circuit.

5. The RF transmitter of claim 4 , wherein the ESD bus is electrically coupled between the first N-type semiconductor material of the SCR and the ESD detection circuit.

6. The RF transmitter of claim 4 , further comprising at least one ESD component that is electrically coupled between the output of the power amplifier and the ESD bus.

7. The RF transmitter of claim 1 , further comprising at least one ESD component that is electrically coupled between the output of the power amplifier and the SCR.

8. The RF transmitter of claim 1 , wherein the ESD detection circuit includes a zener diode and a resistor that are coupled in series between the ESD bus and a second voltage line, wherein the ESD bus has a higher voltage value than the second voltage line, wherein the SCR is triggered from a signal at a node between the zener diode and the resistor responsive to detect the electrostatic discharge on either the ESD bus or the second voltage line.

9. An electrostatic discharge (ESD) protection circuit comprising:

a power amplifier coupled to a first voltage line and to a second voltage line;

a silicon-controlled rectifier (SCR) that is coupled directly to the output of the power amplifier and to the second voltage line;

an ESD detection circuit that is coupled directly to and configured to trigger the SCR in response to detecting an electrostatic discharge on an ESD bus; and

an ESD clamp circuit that is coupled to the first voltage line and to a second voltage line such that the ESD clamp circuit is disposed in parallel with the power amplifier.

10. The ESD protection circuit of claim 9 , wherein the SCR comprises:

an alternating arrangement of a first N-type semiconductor material, a first P-type semiconductor material, a second P-type semiconductor material, a second N-type semiconductor material and a third P-type semiconductor material, wherein shallow trench isolations (STIs) are located at the ends of the alternating arrangement and between the first P-type semiconductor material and the second P-type semiconductor material, wherein the output of the power amplifier, the ESD detection circuit, and a second voltage line are electrically coupled to the first P-type semiconductor material, the second P-type semiconductor material, and the second N-type and third P-type semiconductor material, respectively.

11. The ESD protection circuit of claim 9 , wherein the first P-type and second P-type semiconductor materials are implanted in an N-well and the second P-type, second N-type and third P-type semiconductor materials are implanted in a P-well, wherein both the N-well and the P-well are formed in a P substrate.

12. The ESD protection circuit of claim 10 , wherein the ESD bus is coupled between the SCR and the ESD detection circuit.

13. The ESD protection circuit of claim 12 , further comprising at least one ESD component that is electrically coupled between the output of the power amplifier and the second voltage line.

14. The ESD protection circuit of claim 10 , further comprising at least one ESD component that is electrically coupled between the output of the ESD bus and the first voltage line.

15. The ESD protection circuit of claim 14 , further comprising at least one ESD component that is electrically coupled between the SCR and a second voltage line, wherein the first voltage line has a higher voltage value than the second voltage line.

16. The ESD protection circuit of claim 9 , wherein the ESD detection circuit includes a zener diode and a resistor that are coupled in series between the ESD bus and a second voltage line, wherein the SCR is triggered from a signal at a node between the zener diode and the resistor responsive to detecting the electrostatic discharge on either the ESD bus or the second voltage line.

17. An electronic device comprising:

a power amplifier having an input that is configured to receive and to amplify RF signals and an output that is configured to transmit the amplified RF signals; and

an electrostatic discharge (ESD) protection circuit that is electrically coupled to the output of the power amplifier, wherein the ESD protection circuit includes:

a silicon-controlled rectifier (SCR) that is coupled directly to the output of the power amplifier and to a second voltage line,

an ESD detection circuit that is coupled directly to and is configured to trigger the SCR responsive to detecting an electrostatic discharge on an ESD bus,

an ESD clamp circuit that is coupled to the first voltage line and to the second voltage line such that the ESD clamp circuit is disposed in parallel with power amplifier, ESD detection circuit, and the SCR, and

at least one ESD component coupled between the ESD bus and a node at which the output of the power amplifier and the SCR are coupled directly.

18. The electronic device of claim 17 , wherein the SCR comprises:

an alternating arrangement of a first N-type semiconductor material, a first P-type semiconductor material, a second P-type semiconductor material, a second N-type semiconductor material and a third P-type semiconductor material, wherein shallow trench isolations (STIs) are located at the ends of the alternating arrangement and between the first P-type semiconductor material and the second P-type semiconductor material, wherein the output of the power amplifier, the ESD detection circuit, and a second voltage line are electrically coupled to the first P-type semiconductor material, the second P-type semiconductor material, and the second N-type and third P-type semiconductor material, respectively.

19. The electronic device of claim 17 , wherein the first P-type and first N-type semiconductor materials are implanted in an N-well and the second P-type, second N-type and third P-type semiconductor materials are implanted in a P-well, wherein both the N-well and the P-well are formed in a P substrate.

20. The electronic device of claim 18 , wherein the ESD bus is coupled between the at least one ESD component and the ESD detection circuit.

21. An electrostatic discharge (ESD) protection circuit comprising:

a silicon-controlled rectifier (SCR) that is electrically coupled to the output of a power amplifier;

an ESD detection circuit configured to trigger the SCR in response to detecting an electrostatic discharge on an ESD bus;

an ESD clamp circuit coupled to a first voltage line; and

at least one ESD component that is electrically coupled between the output of the power amplifier and a second voltage line,

wherein the ESD bus is coupled between the SCR and the ESD detection circuit, and

wherein the SCR comprises an alternating arrangement of a first N-type semiconductor material, a first P-type semiconductor material, a second P-type semiconductor material, a second N-type semiconductor material and a third P-type semiconductor material, wherein shallow trench isolations (STIs) are located at the ends of the alternating arrangement and between the first P-type semiconductor material and the second P-type semiconductor material, wherein the output of the power amplifier, the ESD detection circuit, and a second voltage line are electrically coupled to the first P-type semiconductor material, the second P-type semiconductor material, and the second N-type and third P-type semiconductor material, respectively.

22. An electrostatic discharge (ESD) protection circuit comprising:

a silicon-controlled rectifier (SCR) that is electrically coupled to the output of a power amplifier;

an ESD detection circuit configured to trigger the SCR in response to detecting an electrostatic discharge on an ESD bus;

an ESD clamp circuit coupled to a first voltage line;

at least one ESD component that is electrically coupled between the output of the ESD bus and the first voltage line; and

at least one ESD component that is electrically coupled between the SCR and a second voltage line,

wherein the first voltage line has a higher voltage value than the second voltage line, and

wherein the SCR comprises an alternating arrangement of a first N-type semiconductor material, a first P-type semiconductor material, a second P-type semiconductor material, a second N-type semiconductor material and a third P-type semiconductor material, wherein shallow trench isolations (STIs) are located at the ends of the alternating arrangement and between the first P-type semiconductor material and the second P-type semiconductor material, wherein the output of the power amplifier, the ESD detection circuit, and a second voltage line are electrically coupled to the first P-type semiconductor material, the second P-type semiconductor material, and the second N-type and third P-type semiconductor material, respectively.