Semiconductor device and electronic device
All interface pins for transmitting and receiving a signal having a predetermined function of a semiconductor integrated circuit element are formed on an outer periphery of the semiconductor integrated circuit element along one side of the semiconductor integrated circuit element. The one side of the semiconductor integrated circuit element is adjacent to two of sides of a BGA substrate, the two sides being not parallel to the one side. Of balls provided on the BGA substrate, balls electrically connected to the interface pins for transmitting and receiving a signal having a predetermined function are provided between the one side of the semiconductor integrated circuit element and the two sides of the BGA substrate.
1. A semiconductor device comprising:
a semiconductor integrated circuit element; and
a substrate on which the semiconductor integrated circuit element is mounted,
wherein
the semiconductor integrated circuit element is in the shape of a polygonal plate,
the substrate is in the shape of a polygonal plate,
an interface pin or pins for transmitting and receiving a signal having a predetermined function of the semiconductor integrated circuit element are formed on an outer periphery of the semiconductor integrated circuit element along one side of the semiconductor integrated circuit element,
the one side of the semiconductor integrated circuit element is adjacent to two of sides of the substrate, the two sides being not parallel to the one side, and
of electrode terminals provided on the substrate, an electrode terminal or terminals electrically connected to the interface pin or pins for transmitting and receiving a signal having a predetermined function are provided between the one side of the semiconductor integrated circuit element and the two sides of the substrate.
2. The semiconductor device of claim 1 , wherein
the interface pin or pins for transmitting and receiving a signal having a predetermined function are a plurality of memory data IO terminals, a plurality of control signal IO terminals, and a plurality of address IO terminals, and are arranged along the one side of the semiconductor integrated circuit element in the order of the memory data IO terminals, the control signal IO terminals, the address IO terminals, and the memory data IO terminals, or in the order of the memory data IO terminals, the control signal IO terminals, the address IO terminals, the control signal IO terminals, and the memory data IO terminals.
3. The semiconductor device of claim 2 , wherein
of the electrode terminals, electrode terminals electrically connected to the address IO terminals are located at a corner portion formed by the two sides of the substrate, and electrode terminals electrically connected to the memory data IO terminals are located along the two sides with the corner portion being interposed therebetween.
4. The semiconductor device of claim 2 , wherein
a line passing through the angle formed by the two sides of the substrate and intersecting at right angles with the one side of the semiconductor integrated circuit element, passes through a region where the address IO terminals are located.
5. The semiconductor device of claim 1 , wherein
the semiconductor integrated circuit element is in the shape of a rectangular plate.
6. An electronic device comprising:
the semiconductor device of any one of claims 2 - 5 ; and
two memory elements,
wherein
the two memory elements are adjacent to the two sides of the substrate, and
an interconnect between the address IO terminals and address bus terminals of the two memory elements has a T-branched shape.