ZrXHfYSn1-X-YO2 films as high K gate dielectrics
The use of atomic layer deposition (ALD) to form a nanolaminate dielectric of zirconium oxide (ZrO 2 ), hafnium oxide (HfO 2 ) and tin oxide (SnO 2 ) acting as a single dielectric layer with a formula of Zr x Hf y Sn 1-x-y O 2 , and a method of fabricating such a dielectric layer is described that produces a reliable structure with a high dielectric constant (high k). The dielectric structure is formed by depositing zirconium oxide by atomic layer deposition onto a substrate surface using precursor chemicals, followed by depositing hafnium oxide onto the substrate using precursor chemicals, followed by depositing tin oxide onto the substrate using precursor chemicals, and repeating to form the thin laminate structure. Such a dielectric may be used as a gate insulator, a capacitor dielectric, or as a tunnel insulator in non-volatile memories, because the high dielectric constant (high k) provides the functionality of a much thinner silicon dioxide film.
1. A metal oxide semiconductor transistor; comprising:
a semiconductor of a first doping type and a first concentration level;
at least two diffusion regions in a substrate having a second opposite doping type, and a second higher concentration level;
a channel region disposed between to separate the at least two diffusion regions;
a dielectric having a first thickness disposed above the channel region and above at least a portion of the at least two diffusion regions, including at least three different metal oxide materials that include zirconium oxide, hafnium oxide and tin oxide, the materials having an overall dielectric constant of greater than 17.0, and a physical thickness of less than 20 nm; and
a conductive gate electrode material disposed above the dielectric and above at least a portion of the at least two diffusion regions.
2. The metal oxide semiconductor transistor of claim 1 , wherein the at least three different metal oxide materials include a first plurality of individual layers of a first one of the at least three different metal oxide materials, a second plurality of individual layers of a second one of the at least three different metal oxide materials, and a third plurality of individual layers of a third one of the at least three different metal oxide materials.
3. The metal oxide semiconductor transistor of claim 2 , wherein at least some of the individual layers of the at least three different metal oxide materials are in direct contact on a first surface with a different one of the at least three different metal oxide materials, and in direct contact on a second surface with a remaining one of the at least three different metal oxide materials.
4. The metal oxide semiconductor transistor of claim 1 , wherein the dielectric layer has an overall layer composition formula of Zr X Hf Y Sn Z O 2 .
5. The metal oxide semiconductor transistor transistor of claim 4 , wherein X is between 0.70 to 0.85, Y is between 0.05 to 0.25, and Z=1−X−Y.
6. The metal oxide semiconductor transistor of claim 5 , wherein X is about 0.81, Y is about 0.12, and Z is about 0.07.
7. The metal oxide semiconductor transistor of claim 4 , wherein the at least three different metal oxide material individual layers are interleaved such that a local composition of the dielectric film varies between substantially pure ZrO 2 at a bottom portion of the dielectric film disposed near the channel region, to substantially pure HfO 2 at a top portion of the dielectric film disposed near the conductive gate electrode material.
8. The metal oxide semiconductor transistor of claim 1 , wherein a diffusion barrier layer is disposed between a the dielectric layer and the channel region.
9. A transistor, comprising:
a channel region separating a pair of source or drain regions;
an amorphous dielectric over the channel region, the dielectric containing at least one atomic layer deposited dielectric, the atomic layer deposited dielectric including zirconium oxide, hafnium oxide and tin oxide in an integrated circuit; and
a conductive gate located over the dielectric.
10. The transistor of claim 9 , wherein the atomic layer deposited dielectric includes an overall layer dielectric constant of greater than 17.0.
11. The transistor of claim 9 , wherein the atomic layer deposited dielectric includes a physical thickness of less than 20 nm.
12. The transistor of claim 9 , wherein the dielectric layer has an overall layer composition formula of Zr X Hf Y Sn Z O 2 , and wherein X is between 0.70 to 0.85, Y is between 0.05 to 0.25, and Z=1−X−Y.
13. The transistor of claim 12 , wherein X is about 0.81, Y is about 0.12, and Z is about 0.07.
14. The transistor of claim 9 , further including a diffusion barrier between the amorphous dielectric and the channel region.
15. A capacitor, comprising:
a first electrode; and
a second electrode separated from the first electrode by a dielectric, wherein the dielectric includes at least three different metal oxide materials comprising zirconium oxide, hafnium oxide, and tin oxide.
16. The capacitor of claim 15 , wherein the dielectric layer has an overall layer composition formula of Zr X Hf Y Sn Z O 2 , and wherein X is between 0.70 to 0.85, Y is between 0.05 to 0.25, and Z=1−X−Y.
17. The capacitor of claim 15 , wherein X is about 0.81, Y is about 0.12, and Z is about 0.07.
18. A flash memory cell, comprising:
a channel region separating a pair of source or drain regions;
a floating gate located adjacent to the channel region; and
an amorphous dielectric over the channel region, separating the floating gate from the channel region, wherein the dielectric contains at least one atomic layer deposited dielectric, the atomic layer deposited dielectric including zirconium oxide, hafnium oxide and tin oxide in an integrated circuit.
19. The flash memory cell of claim 18 , wherein the atomic layer deposited dielectric includes substantially pure ZrO 2 at a first portion of the dielectric film disposed near the channel region, and substantially pure HfO 2 at a second portion of the atomic layer deposited dielectric.
20. The flash memory cell of claim 19 , wherein the atomic layer deposited dielectric has an overall layer composition formula of Zr X Hf Y Sn Z O 2 , and wherein X is between 0.70 to 0.85, Y is between 0.05 to 0.25, and Z=1−X−Y.
21. The flash memory cell of claim 20 , wherein X is about 0.81, Y is about 0.12, and Z is about 0.07.