Method and structure for shielded gate trench FET
A shielded gate field effect transistor includes a trench extending into a semiconductor region. A shield electrode is in a lower portion of the trench, and is insulated from the semiconductor region by a shield dielectric. The shield dielectric comprises first and second dielectric layers, the first dielectric layer extending between the second dielectric layer and the semiconductor region. The second dielectric layer comprises a material which during oxidation process inhibits growth of oxide along surfaces of the semiconductor region covered by the second dielectric layer. An inter-electrode dielectric overlies the shield electrode, and a gate dielectric lines upper trench sidewalls. A gate electrode is in an upper portion of the trench over the inter-electrode dielectric.
1. A shielded gate field effect transistor, comprising:
a trench extending into a semiconductor region;
a shield electrode disposed in a lower portion of the trench, the shield electrode being insulated from the semiconductor region by a shield dielectric comprising a shield portion of a first dielectric layer, at least a shield portion of a second dielectric layer, and a third dielectric layer,
the first dielectric layer disposed in both the lower portion of the trench and an upper portion of the trench and disposed, at least in part, between the second dielectric layer and the semiconductor region,
the second dielectric layer disposed, at least in part, between the first dielectric layer and the third dielectric layer, the second dielectric layer comprising a material configured to inhibit growth of oxide along a surface of the semiconductor region covered by the second dielectric layer, and
the third dielectric layer disposed in the lower portion of the trench and not disposed in the upper portion of the trench;
an inter-electrode dielectric disposed between the shield electrode and a gate electrode, the gate electrode being disposed in the upper portion of the trench; and
a gate dielectric lining an upper portion sidewall of the trench and comprising a gate portion of the first dielectric layer, the inter-electrode dielectric having a thickness that is greater than a thickness of the gate dielectric.
2. The shielded gate field effect transistor of claim 1 wherein the first dielectric layer comprises an oxide layer and the second dielectric layer comprises a silicon nitride layer.
3. The shielded gate field effect transistor of claim 1 wherein a gate portion of the second dielectric layer is disposed along the upper portion sidewall of the trench, and the gate dielectric includes the gate portion of the second dielectric layer.
4. The shielded gate field effect transistor of claim 3 wherein the first dielectric layer comprises an oxide layer and the second dielectric layer comprises a silicon nitride layer.
5. The shielded gate field effect transistor of claim 1 wherein the first dielectric layer comprises an oxide layer, the second dielectric layer comprises a silicon nitride layer, and the gate dielectric comprises a gate oxide layer.
6. The shielded gate field effect transistor of claim 5 wherein the silicon nitride layer is a first silicon nitride layer, the gate dielectric further comprising a second silicon nitride layer.
7. The shielded gate field effect transistor of claim 1 wherein the semiconductor region comprises:
a drift region of a first conductivity type;
a body region of a second conductivity type extending over the drift region; and
a source region of the first conductivity type disposed in the body region and adjacent to the trench.
8. The shielded gate field effect transistor of claim 7 wherein the gate electrode includes a top surface recessed in the trench to a depth below a top surface of the semiconductor region,
the shielded gate field effect transistor further comprising:
an interconnect layer contacting the source region and the body region; and
a dielectric material disposed over the gate electrode and configured to insulate the gate electrode from the interconnect layer.
9. The shielded gate field effect transistor of claim 7 wherein the semiconductor region includes a substrate of the first conductivity type,
the drift region extends over the substrate, and
the trench extends through the body region and into the drift region.
10. The shielded gate field effect transistor of claim 7 wherein the semiconductor region including a substrate of the second conductivity type,
the drift region extends over the substrate, and
the trench extends through the body region and into the drift region.
11. The shielded gate field effect transistor of claim 1 wherein the first dielectric layer comprises an oxide layer having a thickness within a range of 50-500 Angstroms.
12. The shielded gate field effect transistor of claim 1 wherein the second dielectric layer comprises a silicon nitride layer having a thickness within a range of 100-300 Angstroms.
13. The shielded gate field effect transistor of claim 1 wherein the inter-electrode dielectric comprises a thermal oxide that has a thickness greater than the thickness of the gate dielectric.
14. The shielded gate field effect transistor of claim 1 wherein the first dielectric layer comprises a first oxide layer;
the second dielectric layer comprises a silicon nitride layer; and
the third dielectric layer comprises a second oxide layer.
15. The shielded gate field effect transistor of claim 1 wherein the third dielectric layer has a thickness greater than a thickness of each of the first and second dielectric layers.
16. The shielded gate field effect transistor of claim 1 wherein the third dielectric layer comprises an oxide layer having a thickness within a range of 500-5,000 Angstroms.
17. A shielded gate field effect transistor, comprising:
a semiconductor region comprising a drift region of a first conductivity type and a body region of a second conductivity type extending over the drift region;
a trench extending through the body region and into the drift region;
a source region of the first conductivity type disposed in the body region adjacent the trench;
a first oxide layer disposed along an upper sidewall portion of the trench, a lower sidewall portion of the trench and a bottom portion of the trench;
a silicon nitride layer extending, at least partially, over the first oxide layer disposed along the upper and lower sidewall portions and the bottom portion of the trench;
a second oxide layer extending, at least partially, over the silicon nitride layer along the lower sidewall portion and the bottom portion of the trench;
a shield electrode disposed in a lower portion of the trench, the shield electrode being insulated from the drift region by the first oxide layer, the silicon nitride layer and the second oxide layer;
an inter-electrode dielectric covering the shield electrode; and
a gate electrode disposed in an upper portion of the trench over the inter-electrode dielectric, the gate electrode being insulated from the body region by the first oxide layer and the silicon nitride layer but not the second oxide layer.
18. The shielded gate field effect transistor of claim 17 wherein the semiconductor region further includes a substrate of the first conductivity type, and the drift region extends, at least partially, over the substrate.
19. The shielded gate field effect transistor of claim 17 wherein the semiconductor region further includes a substrate of the second conductivity type, and the drift region extends, at least partially, over the substrate.
20. The shielded gate field effect transistor of claim 17 wherein the inter-electrode dielectric comprises a thermal oxide and has a thickness greater than a combined thicknesses of the first oxide layer and the silicon nitride layer.
21. The shielded gate field effect transistor of claim 17 wherein the second oxide layer has a thickness greater than either of a thickness of the first oxide layer or a thickness of the silicon nitride layer.
22. The shielded gate field effect transistor of claim 17 wherein the first oxide layer has a thickness within a range of 50-500 Angstroms, the silicon nitride layer has a thickness within a range of 100-300 Angstroms, and the second oxide layer has a thickness within a range of 500-5,000 Angstroms.
23. An apparatus comprising:
a trench extending into a semiconductor region;
a shield electrode disposed in a lower portion of the trench;
a first dielectric layer disposed in both the lower portion of the trench and an upper portion of the trench and disposed, at least in part, between a second dielectric layer and the semiconductor region;
the second dielectric layer disposed, at least in part, between the first dielectric layer and a third dielectric layer, and disposed in the lower portion of the trench but not disposed in the upper portion of the trench;
the third dielectric layer disposed in the lower portion of the trench and not disposed in the upper portion of the trench; and
an inter-electrode dielectric disposed between the shield electrode and a gate electrode, the gate electrode being disposed in the upper portion of the trench.
24. The apparatus of claim 23 , wherein
the first dielectric layer comprises a first oxide layer,
the second dielectric layer comprises a silicon nitride layer, and
the third dielectric layer comprises a second oxide layer.