Method to improve bump reliability for flip chip device
A new method is provided for the creation of a solder bump. Conventional methods are initially followed, creating a patterned layer of Under Bump Metal over the surface of a contact pad. A layer of photoresist is next deposited, this layer of photoresist is patterned and developed creating a resist mask having a T-shape opening aligned with the contact pad. This T-shaped opening is filled with a solder compound, creating a T-shaped layer of solder compound on the surface of the layer of UBM. The layer of photoresist is removed, exposing the created T-shaped layer of solder compound, further exposing the layer of UBM. The layer of UBM is etched using the T-shaped layer of solder compound as a mask. Reflow of the solder compound results in creating a solder ball.
1. A solder bump for interconnection of flip chip devices comprising:
a semiconductor surface;
at least one contact pad over said semiconductor surface;
a passivation layer over said semiconductor surface, said passivation layer exposing said at least one contact pad;
an Under-Bump-Metallurgy (UBM) layer over said layer of passivation and said at least one contact pad, lateral dimension of the UBM layer being limited to be within lateral dimension of the at least one contact pad; and
at least one solder compound overlying the UBM layer, wherein the solder compound comprises a flat top surface, a flat bottom surface and convex sidewalls, and the flat top surface is greater than the flat bottom surface before connecting to other components.
2. The solder bump of claim 1 , said Under Bump Metallurgy layer comprising a layer of chromium followed by a layer of copper followed by a layer of gold.
3. The solder bump of claim 1 , said Under Bump Metallurgy layer comprising a plurality of sub-layers of different metallic composition.
4. The solder bump of claim 1 , said passivation layer comprising a plurality of passivation layers.
5. The solder bump of claim 4 , wherein at least one of said plurality of passivation layers is PE Si 3 N 4 , SiO 2 a photosensitive polyimide, phosphorous doped silicon dioxide or titanium nitride.
6. The solder bump of claim 1 , said at least one contact pad on said semiconductor surface being electrically connected with a semiconductor device with at least one conductive line of interconnect or with at least one conductive contact point.
7. The solder bump of claim 1 , further comprising a seed layer having been deposited over said patterned layer of passivation.
8. A solder bump for interconnection of flip chip devices comprising:
a semiconductor surface;
at least one contact pad over said semiconductor surface;
a passivation layer over said semiconductor surface, said passivation layer exposing said at least one contact pad;
an Under-Bump-Metallurgy (UBM) layer over said passivation layer and said at least one contact pad, lateral dimension of the UBM layer being limited to a size approximately the same as lateral dimension of the at least one contact pad; and
at least one solder compound overlying the UBM layer, wherein the solder compound comprises a flat top surface, a flat bottom surface and convex sidewalls, and the flat top surface is greater than the flat bottom surface before connecting to other components.
9. A solder bump for interconnection of flip chip devices comprising:
a semiconductor surface;
at least one contact pad over said semiconductor surface;
a passivation layer over said semiconductor surface, said passivation layer exposing said at least one contact pad;
an Under-Bump-Metallurgy (UBM) layer over said passivation layer and said at least one contact pad; and
at least one solder compound overlying the UBM layer, wherein the solder compound comprises a flat top surface, a flat bottom surface and convex sidewalls, and the flat top surface is greater than the flat bottom surface before connecting to other components.