IP Library Granted Patent US 8,502,304
Granted Patent B2
US 8,502,304 · App. 13/048,938 · Granted Aug 6, 2013

Semiconductor substrate and semiconductor chip

Inventor: Takayuki Hashimoto (Naka-gun, JP)
Assignee: Renesas Electronics Corporation
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Quick Facts
Patent No.
US 8,502,304
App. No.
13/048,938
Granted
Aug 6, 2013
Kind
B2
Abstract

A semiconductor substrate capable of detecting operating current of a MOSFET and diode current in a miniaturized MOSFET such as a trench-gate type MOSFET is provided. A semiconductor substrate includes a main current region and a current sensing region in which current smaller than main current flowing in the main current region flows. The main current region has a source electrode disposed on a main surface, the source electrode being in contact with a p-type semiconductor region (body) and an n + -type semiconductor region (source), and the current sensing region has a MOSFET current detecting electrode and a diode current detecting electrode on a main surface, the MOSFET current detecting electrode being in contact with the p-type semiconductor region (body) and the n + -type semiconductor region (source), the diode current detecting electrode being in contact with the p-type semiconductor region (body).

Claims (9)

1. A semiconductor substrate comprising:

a first semiconductor region on a main surface of a substrate;

a second semiconductor region formed in the first semiconductor region and having a conductivity opposite to that of the first semiconductor region;

a third semiconductor region formed in the second semiconductor region and having the same conductivity as the first semiconductor region;

grooves formed in the first semiconductor region, the second semiconductor region, and the third semiconductor region and extending in a first direction on the main surface of the substrate;

a first insulating film formed in the grooves; and

a first conductor formed on the first insulating film, wherein the semiconductor substrate has a main current region and a current detecting region in which current smaller than main current flowing in the main current region flows,

wherein the main current region has a second conductor disposed on a main surface of the main current region, the second conductor being in contact with the second semiconductor region and the third semiconductor region, and

wherein the current detecting region has a third conductor and a fourth conductor disposed on a main surface of the current detecting region, the third conductor being in direct contact with the second semiconductor region and the third semiconductor region, and the fourth conductor being in direct contact with the second conductor.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 16, 2011
From: HASHIMOTO, TAKAYUKI
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 025964/0346 →
Priority Claims (1)
JP 2010-62141 · Mar 18, 2010 · national
Continuity (1)
Related Publication 20110227069A1 · Sep 22, 2011