Gate driver
A gate driver of a switching element Q 1 includes transistors Q 2 and Q 3 that are totem-pole-connected to both ends of a DC power source Vcc 1 , transistors Q 4 and Q 5 that are totem-pole-connected to both ends of a DC power source Vcc 2 and have emitters connected to the gate of the switching element Q 1 , and a transformer T 1 having a primary winding and a secondary winding. The primary winding is connected to a collector of one of the transistors Q 1 and Q 2 , and through a capacitor, emitters of the transistors Q 1 and Q 2 . The second winding is connected to bases of the transistors Q 4 and Q 5 and the emitters of the transistors Q 4 and Q 5 . A maximum duty cycle of a pulse signal is determined according to a primary winding voltage of the transformer and a forward base-emitter voltage of the transistors Q 4 and Q 5.
1. A gate driver for driving a gate of a switching element, comprising:
a first transistor and a second transistor that are connected in a manner of totem pole to both ends of a first DC power source and have control terminals to which a pulse signal is applied;
a third transistor and a fourth transistor that are connected in a manner of totem pole to both ends of a second DC power source and have first main terminals connected to the gate of the switching element; and
a transformer having a primary winding and a secondary winding, the primary winding being connected to a second main terminal of one of the first and second transistors, and through a capacitor, first main terminals of the first and second transistors, and the second winding being connected to control terminals of the third and fourth transistors and the first main terminals of the third and fourth transistors, wherein
a maximum duty cycle of the pulse signal is determined according to a primary winding voltage of the transformer and a forward control-terminal voltage of the third and fourth transistors.
2. The gate driver of claim 1 , wherein the first and second transistors form a first transistor group, the third and fourth transistors form a second transistor group, and each transistor of at least one of the transistor groups is selected from a group of a FET, a GaN-FET, and an SiC-FET.
3. The gate driver of claim 1 , wherein the first and second transistors, third and fourth transistors, transformer, and capacitor are arranged in an insulated package.