IP Library › Granted Patent US 8,507,902
Granted Patent B2
US 8,507,902 · App. 13/096,094 · Granted Aug 13, 2013

Semiconductor device

Inventor: Kiyoshi Kato (Atsugi, JP)
Assignee: Semiconductor Energy Laboratory Co., Ltd.
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Quick Facts
Patent No.
US 8,507,902
App. No.
13/096,094
Granted
Aug 13, 2013
Kind
B2
Abstract

The invention provides a semiconductor device where data can be written after the production and forgery caused by rewriting of data can be prevented, and which can be manufactured at a low cost using a simple structure and an inexpensive material. Further, the invention provides a semiconductor device having the aforementioned functions, where wireless communication is not blocked by the internal structure. The semiconductor device of the invention has an organic memory provided with a memory cell array including a plurality of memory cells, a control circuit for controlling the organic memory, and a wire for connecting an antenna. Each of the plurality of memory cells has a transistor and a memory element. The memory element has a structure where an organic compound layer is provided between a first conductive layer and a second conductive layer. The second conductive layer is formed in a linear shape.

Claims (75)

1. A semiconductor device comprising:

an organic memory provided with a memory cell array including a plurality of memory cells; and

a control circuit for controlling the organic memory,

wherein each of the plurality of memory cells includes a transistor and a memory element,

wherein the memory element includes a first conductive layer, an organic compound layer, and a second conductive layer, and

wherein the second conductive layer is common for memory elements each in one of the plurality of memory cells and formed in a linear shape.

2. The semiconductor device according to claim 1 ,

wherein the organic compound layer is an electron transporting layer or a hole transporting layer.

3. The semiconductor device according to claim 1 ,

wherein the organic compound layer comprises a material having a resistance that is changed by light irradiation, heating, or an electrical effect.

4. The semiconductor device according to claim 1 ,

wherein the semiconductor device further comprises one or more of a DRAM (Dynamic Random Access Memory), an SRAM (Static Random Access Memory), an FeRAM (Ferroelectric Random Access Memory), a mask ROM (Mask Read Only Memory), a PROM (Programmable Read Only Memory), an EPROM (Electrically Programmable Read Only Memory), an EEPROM (Electrically Erasable Read Only Memory), and a flash memory in addition to the organic memory.

5. The semiconductor device according to claim 1 ,

wherein the semiconductor device further comprises one or more of a power supply circuit, a clock generation circuit, a demodulation/modulation circuit, and an interface circuit in addition to the control circuit.

6. The semiconductor device according to claim 1 ,

wherein the organic memory and the control circuit are provided over a flexible substrate.

7. The semiconductor device according to claim 1 ,

wherein the control circuit includes a thin film transistor.

8. A semiconductor device comprising:

an organic memory provided with a memory cell array including a plurality of memory cells;

a control circuit for controlling the organic memory; and

an antenna,

wherein each of the plurality of memory cells includes a transistor and a memory element,

wherein the memory element includes a first conductive layer, an organic compound layer, and a second conductive layer, and

wherein the second conductive layer is common for memory elements each in one of the plurality of memory cells and formed in a linear shape.

9. The semiconductor device according to claim 8 ,

wherein the organic compound layer is an electron transporting layer or a hole transporting layer.

10. The semiconductor device according to claim 8 ,

wherein the organic compound layer comprises a material having a resistance that is changed by light irradiation, heating, or an electrical effect.

11. The semiconductor device according to claim 8 ,

wherein the semiconductor device further comprises one or more of a DRAM (Dynamic Random Access Memory), an SRAM (Static Random Access Memory), an FeRAM (Ferroelectric Random Access Memory), a mask ROM (Mask Read Only Memory), a PROM (Programmable Read Only Memory), an EPROM (Electrically Programmable Read Only Memory), an EEPROM (Electrically Erasable Read Only Memory), and a flash memory in addition to the organic memory.

12. The semiconductor device according to claim 8 ,

wherein the semiconductor device further comprises one or more of a power supply circuit, a clock generation circuit, a demodulation/modulation circuit, and an interface circuit in addition to the control circuit.

13. The semiconductor device according to claim 8 ,

wherein the organic memory and the control circuit are provided over a flexible substrate.

14. The semiconductor device according to claim 8 ,

wherein the organic memory, the control circuit, and the antenna are formed over a glass substrate.

15. The semiconductor device according to claim 8 ,

wherein the organic memory, the control circuit, and the antenna are formed over a flexible substrate.

16. The semiconductor device according to claim 8 ,

wherein the control circuit includes a thin film transistor.

17. A semiconductor device comprising:

an organic memory provided with a memory cell array including a plurality of memory cells; and

a control circuit for controlling the organic memory,

wherein each of the plurality of memory cells includes a transistor and a memory element,

wherein the memory element includes a first conductive layer, an organic compound layer, and a second conductive layer,

wherein the second conductive layer is common for memory elements each in one of the plurality of memory cells and formed in a linear shape, and

wherein one or both of the first conductive layer and the second conductive layer transmit light.

18. The semiconductor device according to claim 17 ,

wherein the organic compound layer is an electron transporting layer or a hole transporting layer.

19. The semiconductor device according to claim 17 ,

wherein the organic compound layer comprises a material having a resistance that is changed by light irradiation, heating, or an electrical effect.

20. The semiconductor device according to claim 17 ,

wherein the semiconductor device further comprises one or more of a DRAM (Dynamic Random Access Memory), an SRAM (Static Random Access Memory), an FeRAM (Ferroelectric Random Access Memory), a mask ROM (Mask Read Only Memory), a PROM (Programmable Read Only Memory), an EPROM (Electrically Programmable Read Only Memory), an EEPROM (Electrically Erasable Read Only Memory), and a flash memory in addition to the organic memory.

21. The semiconductor device according to claim 17 ,

wherein the semiconductor device further comprises one or more of a power supply circuit, a clock generation circuit, a demodulation/modulation circuit, and an interface circuit in addition to the control circuit.

22. The semiconductor device according to claim 17 ,

wherein the organic memory and the control circuit are provided over a flexible substrate.

23. The semiconductor device according to claim 17 ,

wherein the control circuit includes a thin film transistor.

24. A semiconductor device comprising:

a memory provided with a memory cell array including a plurality of memory cells; and

a circuit for controlling the memory,

wherein each of the plurality of memory cells includes a transistor and a memory element,

wherein the memory element includes a first conductive layer, an organic compound layer, and a second conductive layer, and

wherein the second conductive layer is common for memory elements each in one of the plurality of memory cells and formed in a linear shape.

25. The semiconductor device according to claim 24 , wherein the memory is an organic memory.

26. The semiconductor device according to claim 24 ,

wherein the organic compound layer is an electron transporting layer or a hole transporting layer.

27. The semiconductor device according to claim 24 ,

wherein the organic compound layer comprises a material having a resistance that is changed by light irradiation, heating, or an electrical effect.

28. The semiconductor device according to claim 24 ,

wherein the semiconductor device further comprises one or more of a DRAM (Dynamic Random Access Memory), an SRAM (Static Random Access Memory), an FeRAM (Ferroelectric Random Access Memory), a mask ROM (Mask Read Only Memory), a PROM (Programmable Read Only Memory), an EPROM (Electrically Programmable Read Only Memory), an EEPROM (Electrically Erasable Read Only Memory) and a flash memory.

29. The semiconductor device according to claim 24 ,

wherein the semiconductor device further comprises one or more of a power supply circuit, a clock generation circuit, and a demodulation/modulation circuit.

Priority Claims (1)
JP 2004-351096 · Dec 3, 2004 · national
Continuity (2)
Division 11791615
Related Publication 20110222336A1 · Sep 15, 2011