IP Library › Granted Patent US 8,507,949
Granted Patent B2
US 8,507,949 · App. 13/195,190 · Granted Aug 13, 2013

Semiconductor device

Inventors: Masato Nishimori (Kawasaki, JP); Atsushi Yamada (Kawasaki, JP)
Assignee: Fujitsu Limited
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Quick Facts
Patent No.
US 8,507,949
App. No.
13/195,190
Granted
Aug 13, 2013
Kind
B2
Abstract

A semiconductor device includes a substrate, a carrier transit layer disposed above the substrate, a compound semiconductor layer disposed on the carrier transit layer, a source electrode disposed on the compound semiconductor layer, a first groove disposed from the back of the substrate up to the inside of the carrier transit layer while penetrating the substrate, a drain electrode disposed in the inside of the first groove, a gate electrode located between the source electrode and the first groove and disposed on the compound semiconductor layer, and a second groove located diagonally under the source electrode and between the source electrode and the first groove and disposed from the back of the substrate up to the inside of the carrier transit layer while penetrating the substrate.

Claims (13)

1. A semiconductor device, comprising:

a substrate; a carrier transit layer disposed above the substrate;

a compound semiconductor layer disposed on the carrier transit layer;

a source electrode disposed on the compound semiconductor layer;

a first groove disposed from a back of the substrate up to an inside of the carrier transit layer while penetrating the substrate;

a drain electrode disposed in the inside of the first groove;

a gate electrode located between the source electrode and the first groove and disposed on the compound semiconductor layer; and

a second groove located diagonally under the source electrode and between the source electrode and the first groove and disposed from the back of the substrate up to another inside of the carrier transit layer while penetrating the substrate.

2. The semiconductor device according to claim 1 ,

wherein the drain electrode is disposed at an interface or in the vicinity of an interface between the compound semiconductor layer and the carrier transit layer.

3. The semiconductor device according to claim 1 , further comprising an insulating film disposed on a side surface of the drain electrode.

4. The semiconductor device according to claim 1 , further comprising a stopper layer disposed between the substrate and the carrier transit layer,

wherein the first groove and the second groove penetrate the stopper layer.

Assignments (4)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 17, 2025
From: FUJITSU LIMITED
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 073964/0516 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 27, 2024
From: FUJITSU LIMITED
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 069454/0333 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ADDRESS OF ASSIGNEE PREVIOUSLY RECORDED ON REEL 026800 FRAME 0720. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT OF ASSIGNOR'S INTEREST. Recorded Sep 19, 2011
From: NISHIMORI, MASATO; YAMADA, ATSUSHI
To: FUJITSU LIMITED
Reel/Frame 026954/0090 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 24, 2011
From: NISHIMORI, MASATO; YAMADA, ATSUSHI
To: FUJITSU LIMITED
Reel/Frame 026800/0720 →
Priority Claims (1)
JP 2010-186461 · Aug 23, 2010 · national
Continuity (1)
Related Publication 20120043586A1 · Feb 23, 2012