Precharge signal generation circuit of semiconductor memory apparatus
A precharge signal generation circuit of a semiconductor memory apparatus may comprise a read/write precharge command generation section configured to delay a precharge command by a first delay time set in response to a control signal to generate one of a read precharge command and a write precharge command; and a read/write bank precharge address generation section configured to delay a bank column address strobe signal by a second delay time set in response to the precharge command delayed in the read/write precharge command generation section, and generate one of a read bank precharge address and a write bank precharge address.
1. A precharge signal generation circuit of a semiconductor memory apparatus, comprising:
a read/write precharge command generation section configured to delay a precharge command by a first delay time set in response to a control signal to generate one of a read precharge command and a write precharge command; and
a read/write bank precharge address generation section configured to delay a bank column address strobe signal by a second delay time set in response to the precharge command delayed in the read/write precharge command generation section, and generate one of a read bank precharge address and a write bank precharge address.
2. The precharge signal generation circuit according to claim 1 , further comprising:
a control signal generation section configured to generate the control signal in response to write-related precharge standard time.
3. The precharge signal generation circuit according to claim 1 , further comprising:
a decoder configured to generate a precharge signal in response to the read precharge command, the write precharge command, the read bank precharge address, and the write bank precharge address.
4. The precharge signal generation circuit according to claim 1 , wherein the first delay time is substantially identical to the second delay time.
5. The precharge signal generation circuit according to claim 1 , wherein the read/write precharge command generation section comprises:
a delay pass configured to delay the precharge command by the first delay time in response to the control signal and a clock signal; and
a signal combination part configured to combine the precharge command internally delayed with a write flag signal for defining a write operation, and generate one of the read precharge command and the write precharge command.
6. The precharge signal generation circuit according to claim 5 , wherein the delay pass comprises:
a plurality of flip-flops configured to commonly receive the clock signal and selectively receive the control signal.
7. The precharge signal generation circuit according to claim 1 , wherein the read/write bank precharge address generation section comprises:
a delay pass configured to delay the bank column address strobe signals by the second delay time set in response to the precharge command internally delayed in the read/write precharge command generation section, and generate a read bank column address strobe signal and a write bank column address strobe signal; and
a signal combination part configured to combine the read bank column address strobe signal and the write bank column address strobe signal with a write flag signal for defining a write operation, and generate one of the read bank precharge address and the write bank precharge address.
8. The precharge signal generation circuit according to claim 7 , wherein the delay pass comprises:
a plurality of latches configured to be selectively activated according to the precharge command internally delayed in the read/write precharge command generation section.
9. The precharge signal generation circuit according to claim 3 , wherein one of read with auto-precharge and write with auto-precharge is performed with respect to a specific memory bank of a plurality of memory banks of the semiconductor memory apparatus according to the precharge signal.
10. A precharge signal generation circuit of a semiconductor memory apparatus, comprising:
a first delay pass configured to delay a precharge command by first delay time in response to a control signal and a clock signal;
a second delay pass configured to delay a bank column address strobe signal by a delay time, which is substantially identical to the first delay time, in response to the precharge command delayed in the first delay pass in a unit manner, and generate a bank column address strobe signal;
a signal combination part configured to combine the precharge command delayed in the unit manner with a write flag signal for defining a write operation to generate a write precharge command, and combine the bank column address strobe signal with the write flag signal to generate a write bank precharge address; and
a decoder configured to generate a precharge signal in response to the read precharge command and the write bank precharge address.
11. The precharge signal generation circuit according to claim 10 , further comprising:
a control signal generation section configured to generate the control signal in response to write-related precharge standard time.
12. The precharge signal generation circuit according to claim 10 , wherein the first delay pass comprises:
a plurality of flip-flops configured to commonly receive the clock signal and selectively receive the control signal.
13. The precharge signal generation circuit according to claim 10 , wherein the second delay pass comprises:
a plurality of latches configured to be selectively activated according to the precharge command delayed in the unit manner.
14. The precharge signal generation circuit according to claim 10 , wherein one of read with auto-precharge and write with auto-precharge performed with respect to a specific memory bank of a plurality of memory banks of the semiconductor memory apparatus according to the precharge signal.