IP Library Granted Patent US 8,513,736
Granted Patent B2
US 8,513,736 · App. 13/553,300 · Granted Aug 20, 2013

Semiconductor device

Inventor: Hiroki Fujii (Kanagawa, JP)
Assignee: Renesas Electronics Corporation
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Quick Facts
Patent No.
US 8,513,736
App. No.
13/553,300
Granted
Aug 20, 2013
Kind
B2
Abstract

A field-effect transistor ( 142 ) includes a lowly p-doped region 110 formed on a surface of a substrate ( 102 ), an n-doped drain region 112 and n-doped source region 114 arranged on a surface of the lowly p-doped region 110 , and a device isolation insulating film 132 and device isolation insulating film 134 . Here, the device isolation insulating film 132 is formed greater in film thickness than the device isolation insulating film 134 ; and in the n-doped source region 114 , the peak concentration section having a highest dopant concentration is formed in a deeper position than in the n-doped drain region 112.

Claims (14)

1. A semiconductor device comprising:

a substrate having a first semiconductor region of a first conduction type in a surface portion of the substrate;

a second semiconductor region of a second conduction type formed in a part of the surface of the first semiconductor region;

a third semiconductor region of the second conduction type formed in a part of the surface of the first semiconductor region;

a fourth semiconductor region of the first conduction type formed in a part of the surface of the first semiconductor region;

a gate insulating film formed so as to cover the surface of the first semiconductor region between the second semiconductor region and the third semiconductor region;

a gate electrode formed over gate insulating film;

a buried semiconductor region of the second conduction type formed under the first semiconductor region;

a sinker layer of the second conduction type formed over the buried semiconductor region and extending from the buried semiconductor region to the surface of the substrate such that the first semiconductor region is surrounded by the sinker layer and the buried semiconductor region,

the sinker layer electrically connected to the second semiconductor region; and

a first isolating insulating film lying between the gate electrode and the second semiconductor region and having a thickness greater than a thickness of the gate insulating film such that an edge of the gate electrode extends over the first isolating insulating film.

2. The semiconductor device according to claim 1 , further comprising:

a second isolating insulating film lying between the gate electrode and the third semiconductor region and having a thickness greater than a thickness of the gate insulating film.

3. The semiconductor device according to claim 2 , wherein the thickness of the first isolating insulating film is greater than the thickness of the second isolating insulating film.

Assignments (3)
CHANGE OF ADDRESS Recorded Nov 29, 2017
From: RENESAS ELECTRONICS CORPORATION
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 044928/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 20, 2012
From: FUJII, HIROKI
To: NEC ELECTRONICS CORPORATION
Reel/Frame 028594/0052 →
CHANGE OF NAME Recorded Jul 20, 2012
From: NEC ELECTRONICS CORPORATION
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 028594/0109 →
Priority Claims (1)
JP 2008-253366 · Sep 30, 2008 · national
Continuity (3)
Continuation 13347180 · Jan 10, 2012
Division 12568906 · Sep 29, 2009
Related Publication 20120280321A1 · Nov 8, 2012