Low-voltage structure for high-voltage electrostatic discharge protection
An electrostatic discharge (ESD) protected device may include a substrate, an N+ doped buried layer, an N-type well region and a P-type well region. The N+ doped buried layer may be disposed proximate to the substrate. The N-type well region may be disposed proximate to a portion of the N+ doped buried layer to form a collector region. The P-type well region may be disposed proximate to remaining portions of the N+ doped buried layer and having at least a P+ doped plate corresponding to a base region and distributed segments of N+ doped plates corresponding to an emitter region.
1. An electrostatic discharge (ESD) protected device comprising:
a substrate;
an N+ doped buried layer disposed proximate to the substrate, and including first and second portions;
an N-type well region disposed proximate to the first portion of the N+ doped buried layer to form a collector region; and
a P-type well region disposed proximate to the second portion of the N+ doped buried layer, the P-type well region having at least a P+ doped plate corresponding to a base region, and distributed segments of N+ doped plates corresponding to an emitter region,
wherein the distributed segments of N+ doped plates are separated from each other by respective portions of the P-type well and a respective gate structure is disposed proximate each respective portion of the P-type well.
2. The ESD protected device of claim 1 , wherein the N-type well region includes two portions disposed on opposite sides of the P-type well region.
3. The ESD protected device of claim 1 , wherein the gate structures each include a gate oxide and polysilicon enabling provision of a bias signal to thereby enable early turn on of the device for ESD protection due to ESD current dissipation over distributed effective transistors.
4. The ESD protected device of claim 1 , wherein the collector region and the base region are concentric geometric shapes.
5. The ESD protected device of claim 4 , wherein the collector region, the base region, the emitter region and a gate region disposed between portions of the emitter region to form the distributed segments of N+ doped plates are concentric circles.
6. The ESD protected device of claim 4 , wherein the collector region, the base region, and the emitter region are concentric circles and a gate region is defined by lines radially extending through a center of the emitter region with substantially equal angular separation therebetween to form the distributed segments of N+ doped plates.
7. The ESD protected device of claim 4 , further comprising portions of the P-type well that divide the emitter region into the distributed segments of N+ doped plates, wherein the collector region and the base region enclose the respective portions of the P-type well.
8. The ESD protected device of claim 7 , wherein said portions comprise a plurality of linearly extending portions disposed between and parallel to respective linearly extending portions of the emitter region, the portions dividing the emitter region into the distributed segments of N+ doped plates.
9. The ESD protected device of claim 7 , wherein the gate region comprises a grid-like arrangement including a plurality of linearly extending portions, a first group of the linearly extending portions being disposed substantially perpendicular to a second group of the linearly extending portions to divide the emitter region into the distributed segments of N+ doped plates formed in columns and rows within the grid-like arrangement.
10. The ESD protected device of claim 1 , wherein the N-type well region includes N-implant material.
11. The ESD protected device of claim 1 , wherein the P-type well region comprises a P-type well stacked with a P+ buried layer or a P-implant.
12. The ESD protected device of claim 1 , wherein the N+ doped buried layer comprises epitaxially formed N-type material or a deep N-type well.
13. The ESD protected device of claim 1 , wherein the N+ doped buried layer comprises multiple stacked N+ buried layers.
14. The ESD protected device of claim 1 , wherein the distributed segments of N+ doped plates are each associated with a respective one of a plurality of separate ESD current dissipation paths.
15. An electrostatic discharge (ESD) protected device comprising:
a substrate;
an N+ doped buried layer disposed proximate to the substrate, and including first and second portions;
an N-type well region disposed proximate to the first portion of the N+ doped buried layer to form a collector region;
a P-type well region disposed proximate to the second portion of the N+ doped buried layer, the P-type well region having at least a P+ doped plate corresponding to a base region, and distributed segments of N+ doped plates corresponding to an emitter region, wherein the distributed segments of N+ doped plates are each associated with a respective one of a plurality of separate ESD current dissipation paths; and
a gate disposed between each of the distributed segments of N+ doped plates to enable early turn on of each respective one of the plurality of separate ESD current dissipation paths during an ESD event.
16. An electrostatic discharge (ESD) protected device comprising:
a substrate;
an N+ doped buried layer disposed proximate to the substrate, and including first and second portions;
an N-type well region disposed proximate to the first portion of the N+ doped buried layer to form a collector region; and
a P-type well region disposed proximate to the second portion of the N+ doped buried layer, the P-type well region having at least a P+ doped plate corresponding to a base region, and distributed segments of N+ doped plates corresponding to an emitter region, wherein the distributed segments of N+ doped plates are separated from each other by respective portions of the P-type well, wherein a respective gate structure is disposed proximate each respective portion of the P-type well.
17. The ESD protected device of claim 16 , wherein the gate structures each include a gate oxide and polysilicon enabling provision of a bias signal to thereby enable early turn on of the device for ESD protection due to ESD current dissipation over distributed effective transistors.