Communication system, data transmitter, and data receiver capable of detecting incorrect receipt of data
A transmitter cyclic pattern having a pattern length of N bits is generated and converted into an M-bit transmitter parallel data stream, where N≠M. A bit-sequence altered transmitter parallel data stream is generated by performing a transmitter altering process, converted into a serial data and transmitted together with a clock signal. The serial data is received and converted into an M-bit receiver parallel data stream, and a bit-sequence restored parallel data stream is generated by performing a process opposite to the transmitter altering process. A receiver cyclic pattern is generated by using bits in the bit-sequence restored parallel data stream and converted into an M-bit reference parallel data stream, and a bit-sequence altered reference parallel data stream is generated by performing a process same as the transmitter altering process and compared with the received parallel data to test if the data is correctly received.
1. A communication system comprising:
a data transmitter including:
a transmitter cyclic pattern generating circuit that generates a transmitter cyclic pattern having a pattern length of N bits and converts the transmitter cyclic pattern into a M-bit transmitter parallel data stream, where each of N and M is an integer larger than one and N and M are different with each other;
a transmitter bit-sequence altering circuit that alters a sequence of bits in each word of the transmitter parallel data stream by performing a transmitter altering process including replacing specified ones of the bits in each word of the transmitter parallel data stream with each other so that a bit-sequence altered transmitter parallel data stream is generated; and
a serializer that converts the bit-sequence altered transmitter parallel data stream into a serial data in synchronous with a clock signal and transmits the serial data together with the clock signal; and
a data receiver including:
a de-serializer that receives the serial data and the clock signal, and converts the serial data into a M-bit receiver parallel data stream in synchronous with the clock signal;
a receiver bit-sequence altering circuit that alters a sequence of bits in each word of the receiver parallel data stream by performing a receiver altering process opposite to the transmitter altering process so that a bit-sequence restored parallel data stream is generated;
a receiver cyclic pattern generating circuit having the same construction as the transmitter cyclic pattern generating circuit, the receiver cyclic pattern generating circuit generates a reference cyclic pattern by using bits in the bit-sequence restored parallel data stream as initial values and converts the reference cyclic pattern into a M-bit reference parallel data stream; and
a comparing and checking circuit that compares one of (i) the receiver parallel data stream with a bit-sequence altered reference parallel data stream, and (ii) the bit-sequence restored parallel data stream with the reference parallel data stream, and generates a bit-error detection signal when the serial data is not received correctly, wherein
when the comparing and checking circuit compares the receiver parallel data stream with the bit-sequence altered reference parallel data stream, the data receiver further includes a second bit-sequence altering circuit that alters a sequence of bits in each word of the reference parallel data stream by performing a second altering process same as the transmitter altering process so that the bit-sequence altered reference parallel data stream is generated.
2. The system according to claim 1 , wherein the receiver cyclic pattern generating circuit generates the reference cyclic pattern by using bits in a first word of the bit-sequence restored parallel data stream.
3. The system according to claim 1 , wherein the serial data has a cyclic pattern having an altered pattern length different from N bits.
4. The system according to claim 1 , wherein the serial data has a cyclic pattern having an altered pattern length of N×M bits.
5. The system according to claim 1 , wherein the specified ones of the bits include at least one of a most significant bit and a least significant bit.
6. The system according to claim 1 , wherein the transmitter altering process includes reversing the bit sequence from a most significant bit to a least significant bit in each word.
7. A data receiver comprising:
a de-serializer that receives a serial data and a clock signal and converts the serial data into a M-bit receiver parallel data stream in synchronous with the clock signal;
a receiver bit-sequence altering circuit that alters a sequence of bits in each word of the receiver parallel data stream by performing a first altering process including replacing specified ones of the bits in each word of the receiver parallel data stream with each other so that a bit-sequence restored parallel data stream is generated;
a receiver cyclic pattern, generating circuit that generates a reference cyclic pattern having a pattern length of N bits by using bits in the bit-sequence restored parallel data stream as initial values, where each of N and M is an integer larger than one and N and M are different with each other, the receiver cyclic pattern generating circuit further converts the reference cyclic pattern into a M-bit reference parallel data stream; and
a comparing and checking circuit that compares one of (i) the receiver parallel data stream with a bit-sequence altered reference parallel data stream, and (ii) the bit-sequence restored parallel data stream with the reference parallel data stream, and generates a bit-error detection signal when the serial data is not received correctly, wherein
when the comparing and checking circuit compares the receiver parallel data stream with the bit-sequence altered reference parallel data stream, the data receiver further includes a second bit-sequence altering circuit that alters a sequence of bits in each word of the reference parallel data stream by performing a second altering process opposite to the first altering process so that the bit-sequence altered reference parallel data stream is generated.
8. The data receiver according to claim 7 , wherein the receiver cyclic pattern generating circuit generates the reference cyclic pattern by using bits in a first word of the bit-sequence restored parallel data stream.
9. The data receiver according to claim 7 , wherein the serial data has a cyclic pattern having an altered pattern length different from N bits.
10. The data receiver according to claim 7 , wherein the serial data has a cyclic pattern having an altered pattern length of N×M bits.
11. The data receiver according to claim 7 , wherein the specified ones of the bits include at least one of a most significant bit and a least significant bit.
12. The data receiver according to claim 7 , wherein the first altering process includes reversing the bit sequence from a most significant bit to a least significant bit.