Integrated circuit with coupled processing cores
A processing system on an integrated circuit includes a group of processing cores. A group of dedicated random access memories are severally coupled to one of the group of processing cores or shared among the group. A star bus couples the group of processing cores and random access memories. Additional layer(s) of star bus may couple many such clusters to each other and to an off-chip environment.
1. A processing system comprising:
a plurality of processing cores on an integrated circuit coupled together; and
a plurality of random access memories on the integrated circuit, each of the plurality of random access memories dedicated to one of the plurality of processing cores;
wherein a first group of the plurality of processing cores is coupled together for direct communication with one another by a first star bus.
2. The system of claim 1 , wherein a second group of the plurality of processing cores is coupled together by a second star bus and coupled to the first group of the plurality of processing cores by a third star bus.
3. The system of claim 2 , further including a shared random access memory coupled to the second star bus.
4. The system of claim 1 , further including a shared random access memory coupled to the first star bus.
5. The system of claim 1 , wherein the first star bus comprises a unidirectional bus.
6. The system of claim 1 , wherein one of the plurality of processing cores is disabled when it tests defective.
7. The system of claim 6 wherein disabling the processing core includes inactivating the processing core.
8. The system of claim 1 , wherein each of the plurality of processing cores further includes a level 0 cache operable to receive data from others of the plurality of processing cores through the first star bus.
9. A processing system, comprising:
a group of processing cores on an integrated circuit;
a group of dedicated random access memories on the integrated circuit, each of the dedicated random access memories directly coupled to one of the group of processing cores; and
a star bus coupling to the group of processing cores configured to provide direct communication between the processing cores.
10. The system of claim 9 , further including a shared random access memory coupled to the star bus.
11. The system of claim 10 , wherein the shared random access memory comprises interleaved random access memory.
12. The system of claim 9 , further including a second group of processing cores coupled to the group of processing cores by a second star bus.
13. The system of claim 12 , wherein in the second group of processing cores are coupled together by a third star bus.
14. The system of claim 9 , wherein each of the group of processing cores comprises an isolation system.
15. The system of claim 14 , wherein each of the group of processing cores comprises an isolation system that may inactivated.
16. The system of claim 9 , where in the star bus comprises a unidirectional bus.
17. A processing system, comprising:
a group of processing cores on an integrated circuit; and
a star bus coupling the group of processing cores together in direct communication with one another.
18. The system of claim 17 , further including a group of dedicated random access memories, each of the dedicated random access memories directly coupled to one of the processing cores.
19. The system of claim 18 , further including a shared random access memory coupled to the star bus.
20. The system of claim 19 , wherein the shared random access memory comprises interleaved random access memory.
21. The system of claim 20 , wherein each of the group of processing cores is fusable.
22. The system of claim 21 , wherein fusing a processing core is operable to-inactivate the processing core.
23. The system of claim 17 , further including a plurality of groups of processing cores coupled to the first group of processing cores by a second star bus.