IP Library › Granted Patent US 8,518,789
Granted Patent B2
US 8,518,789 · App. 13/064,347 · Granted Aug 27, 2013

Integrated electronic device and method of making the same

Inventors: Xiaoyu Mi (Kawasaki, JP); Yoshihiro Mizuno (Kawasaki, JP); Tsuyoshi Matsumoto (Kawasaki, JP); Hisao Okuda (Kawasaki, JP); Satoshi Ueda (Kawasaki, JP); Takeo Takahashi (Nagano, JP)
Assignees: Fujitsu Limited; Taiyo Yuden Co., Ltd.
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Quick Facts
Patent No.
US 8,518,789
App. No.
13/064,347
Granted
Aug 27, 2013
Kind
B2
Abstract

An integrated electronic device includes a substrate, passive components, pads for external connection, and three-dimensional wiring. The passive components includes a multi-stage coil inductor provided on the substrate. The multi-stage coil inductor has a plurality of coils disposed in several layers. Mutually adjacent coil wires are spaced-apart from each other. The three-dimensional wiring includes a first wiring portion which extends on the substrate, a second wiring portion which extends off the substrate but along the substrate, and a third wiring portion connecting with the first wiring portion and the second wiring portion.

Claims (17)

1. A method of making an integrated electronic device, the method comprising the steps of:

forming a lower conductive portion by electroplating;

forming a first resist pattern having an opening for formation of an upper conductive portion on the lower conductive portion, the opening allowing part of the lower conductive portion to expose;

forming a seed layer over a surface of the first resist pattern and a surface of the lower conductive portion exposed in the opening;

forming a second resist pattern on the first resist pattern, the second resist pattern being formed with an opening;

forming the upper conductor portion by electroplating in the opening of the second resist pattern;

removing the second resist pattern;

removing the seed layer; and

removing the first resist pattern.

2. The method according to claim 1 , wherein the opening of the second pattern is formed above a region in which the lower conductive portion is exposed from the opening of the first resist pattern and a part of the first resist pattern.

3. The method according to claim 1 , wherein:

the lower conductive portion includes a first coil;

the upper conductive portion includes a second coil; and

removing the first resist pattern includes spacing the first coil and the second coil apart from each other by a gap in a direction in which the first coil and the second coil are staked.

4. The method according to claim 3 , wherein:

the lower conductive portion includes the first coil, at least a part of an external connection and a part of three-dimensional wiring; and

the upper conductive portion includes the second coil and an other part of the three-dimensional wiring.

Priority Claims (1)
JP 2005-252596 · Aug 31, 2005 · national
Continuity (2)
Division 11509577 · Aug 25, 2006
Related Publication 20110171806A1 · Jul 14, 2011