IP Library Granted Patent US 8,519,532
Granted Patent B2
US 8,519,532 · App. 13/230,223 · Granted Aug 27, 2013

Semiconductor device including cladded base plate

Inventors: Andreas Lenniger (Anroechte, DE); Andre Uhlemann (Dortmund, DE); Olaf Hohlfeld (Warstein, DE)
Assignee: Infineon Technologies AG
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Quick Facts
Patent No.
US 8,519,532
App. No.
13/230,223
Granted
Aug 27, 2013
Kind
B2
Abstract

A semiconductor device includes a semiconductor chip coupled to a substrate and a base plate coupled to the substrate. The base plate includes a first metal layer clad to a second metal layer. The second metal layer is deformed to provide a pin-fin or fin cooling structure.

Claims (34)

1. A semiconductor device comprising:

a semiconductor chip coupled to a substrate; and

a base plate coupled to the substrate such that the substrate is between the semiconductor chip and the base plate, the base plate comprising a first metal layer directly clad to a second metal layer, the second metal layer deformed to provide a planar portion and a pin-fin or fin cooling structure extending from the planar portion,

wherein the first metal layer comprises a first material and the second metal layer comprises a second material different from the first material, and

wherein the substrate comprises a ceramic layer, a third metal layer directly coupled to a first side of the ceramic layer, and a fourth metal layer directly coupled to a second side of the ceramic layer opposite the first side.

2. The semiconductor device of claim 1 , wherein the first metal layer comprises copper and the second metal layer comprises aluminum.

3. The semiconductor device of claim 1 , wherein the first metal layer has a thickness between 2.5 mm and 10 mm and the second metal layer has a thickness between 2.5 mm and 10 mm.

4. The semiconductor device of claim 1 , further comprising:

a fifth metal layer clad to the first metal layer opposite the second metal layer.

5. The semiconductor device of claim 4 , wherein the fifth metal layer has a thickness between 1 μm and 0.1 mm.

6. The semiconductor device of claim 4 , wherein the fifth metal layer comprises one of silver and palladium.

7. The semiconductor device of claim 6 , further comprising:

one of a diffusion soldered joint and a sintered joint between the substrate and the fifth metal layer.

8. The semiconductor device of claim 4 , wherein the fifth metal layer comprises aluminum.

9. The semiconductor device of claim 8 , wherein the fifth metal layer is structured to provide a solder stop layer, the semiconductor device further comprising a soldered joint between the substrate and the first metal layer.

10. A semiconductor device comprising:

a first metallized ceramic substrate comprising a ceramic layer, a first metal layer directly coupled to a first side of the ceramic layer, and a second metal layer directly coupled to a second side of the ceramic layer opposite the first side of the ceramic layer;

a first semiconductor chip coupled to a first side of the first metallized ceramic substrate; and

a base plate coupled to a second side of the first metallized ceramic substrate, the second side of the first metallized ceramic substrate opposite the first side of the first metallized ceramic substrate, the base plate comprising a first layer comprising copper clad to a second layer comprising aluminum, the second layer deformed to provide a planar portion and a pin-fin or fin cooling structure.

11. The semiconductor device of claim 10 , further comprising:

a second semiconductor chip coupled to the first side of the first metallized ceramic substrate.

12. The semiconductor device of claim 10 , further comprising:

a second metallized ceramic substrate; and

a second semiconductor chip coupled to a first side of the second metallized ceramic substrate,

wherein the base plate is coupled to a second side of the second metallized ceramic substrate, the second side opposite the first side.

13. The semiconductor device of claim 10 , further comprising:

a cooling chamber including an inlet and an outlet, the cooling chamber surrounding the cooling structure;

a frame attached to the base plate;

potting surrounding the semiconductor chip and the substrate; and

a cap over the potting.

14. The semiconductor device of claim 10 , further comprising:

a power terminal electrically coupled to the first semiconductor chip; and

a control terminal electrically coupled to the first semiconductor chip,

wherein the power terminal and the control terminal have the same dimensions.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 12, 2011
From: LENNIGER, ANDREAS; UHLEMANN, ANDRE; HOHLFELD, OLAF
To: INFINEON TECHNOLOGIES AG
Reel/Frame 026887/0646 →
Continuity (1)
Related Publication 20130062750A1 · Mar 14, 2013