IP Library Granted Patent US 8,519,539
Granted Patent B2
US 8,519,539 · App. 13/238,570 · Granted Aug 27, 2013

Metal wire for a semiconductor device formed with a metal layer without voids therein and a method for forming the same

Inventors: Dong Ha Jung (Kyoungki-do, KR); Baek Mann Kim (Kyoungki-do, KR); Soo Hyun Kim (Seoul, KR); Young Jin Lee (Kyoungki-do, KR); Sun Woo Hwang (Kyoungki-do, KR); Jeong Tae Kim (Kyoungki-do, KR)
Assignee: Hynix Semiconductor Inc.
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Quick Facts
Patent No.
US 8,519,539
App. No.
13/238,570
Granted
Aug 27, 2013
Kind
B2
Abstract

A metal wiring of a semiconductor device includes a semiconductor substrate; an insulating layer provided with a damascene pattern formed over the semiconductor substrate; a diffusion barrier layer which contains a RuO 2 layer formed on a surface of the damascene pattern and an Al deposit-inhibiting layer formed on a portion of the RuO 2 layer in both-side upper portion of the damascene pattern; and a wiring metal layer including Al formed on the diffusion barrier layer by MOCVD method in order to fill the damascene pattern.

Claims (10)

1. A semiconductor device having a metal wiring comprising:

a semiconductor substrate;

an insulating layer provided with a damascene pattern formed over the semiconductor substrate;

a diffusion barrier layer which contains a Ruthenium oxide (RuO2) layer formed on a surface of lower portion of the damascene pattern and an Al deposit-inhibiting layer formed on a surface of upper portion of the damascene pattern excluding a surface of the lower portion of the damascene pattern, and

a wiring metal layer including aluminum (Al) formed on the diffusion barrier layer by a metal organic chemical vapor deposition (MOCVD) method in order to fill the damascene pattern.

2. The semiconductor device according to claim 1 , wherein the damascene pattern is of single type including a trench or dual type including a via-hole and the trench.

3. The semiconductor device according to claim 1 , wherein the RuO 2 layer has a thickness which is 5 to 10% of a width of the damascene pattern.

4. The semiconductor device according to claim 1 , wherein the Al deposit-inhibiting layer comprises a titanium dioxide (TiO2) layer and an aluminum oxide (Al2O3) layer.

5. The semiconductor device according to claim 4 , wherein the Al deposit-inhibiting layer has a thickness which is 5 to 10% of a width of the damascene pattern.

6. The semiconductor device according to claim 1 , wherein the wiring metal layer including Al comprises a stacked layer of an Al layer and an Al layer including copper (Cu).

Priority Claims (1)
KR 10-2006-0137200 · Dec 28, 2006 · national
Continuity (2)
Division 11756005 · May 31, 2007
Related Publication 20120007240A1 · Jan 12, 2012