Analog-digital converter, image sensor system and camera device

1. An analog-digital converter comprising:

a reference signal generation circuit for generating a reference signal whose voltage value increases or decreases over time;

n (n is an integer of 2 or more) comparators arranged in a first direction with a predetermined cell pitch and corresponding respectively to n input voltages, each comparator comparing the voltage value of the reference signal with the input voltage corresponding to the comparator;

n counters corresponding respectively to the n comparators, each counter performing a count operation in synchronism with a predetermined clock so as to output a count value at a point when an output of the comparator corresponding to the counter is inverted; and

n digital memories corresponding respectively to the n counters, each digital memory storing the count value output from the counter corresponding to the digital memory, wherein each of the n comparators includes first and second differential transistors to which the reference signal and the input voltage corresponding to the comparator are given, respectively,

the first differential transistor is formed by p (p is an integer of 2 or more) first unit transistors connected in series, the references signal being given to gates of the p first unit transistors connected in series,

the second differential transistor is formed by p second unit transistors connected in series, the input voltage being given to gates of the p second unit transistors connected in series, and

the first p unit transistors are all NMOS transistors or all PMOS transistors, and the second p unit transistors are all NMOS transistors or all PMOS transistors.

2. The analog-digital converter of claim 1 , wherein

in each of the n comparators, the p first unit transistors and the p second unit transistors are arranged in a second direction perpendicular to the first direction so that a channel length direction thereof matches the first direction, and

a channel length of each of the p first unit transistors and the p second unit transistors is shorter than a cell pitch width that is equivalent to a length of the cell pitch in the first direction.

3. The analog-digital converter of claim 2 , wherein

in each of the n comparators, the p second unit transistors are arranged in line symmetry with the p first unit transistors with respect to a reference line which is a straight line extending in the second direction so as to pass through a reference point within the cell pitch of the comparator.

4. The analog-digital converter of claim 3 , wherein

a k-th (1≦k≦p) first unit transistor and a k-th second unit transistor included in each of the n comparators are arranged along the same straight line in the first direction, and

a channel length of each of the p first unit transistors and the p second unit transistors is shorter than ½ the cell pitch width.

5. The analog-digital converter of claim 3 , wherein

p first unit transistors and p second unit transistors included in each of the n comparators are arranged so as not to be adjacent in the first direction to any of p first unit transistors and p second unit transistors included in another adjacent comparator.

6. The analog-digital converter of claim 2 , wherein

in each of the n comparators, the p second unit transistors are arranged in point symmetry with the p first unit transistors with respect to a reference point within the cell pitch of the comparator.

7. The analog-digital converter of claim 6 , wherein

a k-th (1≦k≦p) first unit transistor and a k-th second unit transistor included in each of the n comparators are arranged along the same straight line in the first direction, and

a channel length of each of the p first unit transistors and the p second unit transistors is shorter than the cell pitch width.

8. The analog-digital converter of claim 6 , wherein

p first unit transistors and p second unit transistors included in each of the n comparators are arranged so as not to be adjacent in the first direction to any of p first unit transistors and p second unit transistors included in another adjacent comparator.

9. The analog-digital converter of claim 1 , wherein

the p first unit transistors have the same channel length, and

the p second unit transistors have the same channel length.

10. The analog-digital converter of claim 1 , wherein

the p first unit transistors have different channel lengths, and

the p second unit transistors have different channel lengths.

11. The analog-digital converter of claim 1 , wherein

each of the n comparators further includes a current source transistor for supplying a reference current to the first and second differential transistors, and

the current source transistor is formed by a plurality of unit transistors connected in series whose gates are given a bias voltage for supplying the reference current.

12. The analog-digital converter of claim 1 , further comprising

n amplifiers arranged in the first direction with a predetermined cell pitch and corresponding respectively to the n input voltages, each amplifier amplifying the input voltage corresponding to the amplifier and supplying the amplified input voltage to the comparator corresponding to the amplifier, wherein

each of the n amplifiers includes a current source transistor for supplying a predetermined current, and

the current source transistor included in each of the n amplifiers is formed by a plurality of unit transistors connected in series whose gates are given a bias voltage for supplying the predetermined current.

13. An image sensor system comprising:

n×m pixel portions arranged in a two-dimensional matrix of n columns by m rows, each pixel portion generating a charge according to an amount of incident light thereupon;

a vertical scanning circuit for selecting the n×m pixel portions row by row;

n readout circuits corresponding respectively to n pixel columns of the n×m pixel portions, each readout circuit generating a pixel voltage according to the charge generated by one of the n pixel portions selected by the vertical scanning circuit that corresponds to the readout circuit;

the analog-digital converter of claim 1 for converting the n pixel voltages generated by the n readout circuits to n digital values; and

a horizontal scanning circuit for successively transferring the n digital values obtained by the analog-digital converter as captured data.

14. The image sensor system of claim 13 , wherein

each of the n readout circuits includes a current source transistor which forms a source follower circuit together with a pixel portion corresponding to the readout circuit, and

the current source transistor included in each of the n readout circuits is formed by a plurality of unit transistors connected in series whose gates are given a reference voltage for supplying a readout current.

15. A camera device comprising:

the image sensor system of claim 13 ; and

a data processing circuit for processing the captured data transferred from the image sensor system.