Multi-value logic signaling in multi-functional circuits
Methods and circuits provide function-appropriate signaling to multi-functional circuits on a constrained set of communication lines. A first communication line receives digital signals. The second communication line is employed for digital signaling related to a first function. In further steps, the method comprises initiating, based on a multi-value logic digital signal on the first communication line, an activation process that generates a second-function activation signal. Upon receipt of the second-function activation signal, the second communication line is employed for digital signaling related to a second function. Preferred activation processes involve monitoring the second communication line for a digital signature and sending the activation signal upon detection of an appropriate signature.
1. A method comprising:
receiving a digital signal on a first pin of an integrated circuit;
employing a second pin of the integrated circuit for digital signaling related to a first function during a first mode of operation;
activating a digital signal signature detection circuit in response to the received digital signal on the first pin being a multi-value logic digital signal;
detecting a digital signal signature from the digital signal signature detection circuit; and
employing, in response to the detecting the digital signal signature, the second pin for digital signaling related to a second function associated with a second mode of operation, different than the first mode of operation,
wherein the pins of the integrated circuit are configured based on an industrial standard specifying the function of the pins when the second function is not employed.
2. The method of claim 1 , wherein activating comprises monitoring the first pin for the multi-value logic digital signal.
3. The method of claim 1 , wherein, upon receiving the multi-value logic digital signal on the first pin, sending an activation signal to the digital signal signature detection circuit.
4. The method of claim 1 , further comprising monitoring the second pin for the digital signal signature.
5. The method of claim 1 , wherein the multi-value logic digital signal strength falls between a minimum binary signal strength and a maximum binary signal strength.
6. The method of claim 1 , wherein the multi-value logic digital signal strength falls below a minimum binary signal strength or above a maximum binary signal strength.
7. The method of claim 1 , wherein employing the second pin for digital signaling is related to the first function if the digital signal signature is not detected.
8. The method of claim 1 , further comprising reverting, upon detection of a deactivation digital signal on the first pin, to employing the second pin for digital signaling related to the first function.
9. The method of claim 1 , wherein the integrated circuit further comprises a memory device.
10. An integrated circuit comprising a pin layout based on an industrial standard that specifies a function of each pin of the integrated circuit, the integrated circuit comprising:
binary logic circuit configured to receive input on a first pin as binary signaling;
a first function circuit configured to receive data on a second pin related to a first function activation signal;
an activation portion configured to monitor the first pin for multi-value logic signaling of activation;
the activation portion further configured to generate a second function activation signal upon detection of the multi-value logic signaling of activation; and
a second function circuit configured to receive the second function activation signal and to employ the second pin for digital signaling related to a second function, different than the first function.
11. The integrated circuit of claim 10 , wherein the activation portion comprises a multi-value logic receiver configured to monitor the first pin for multi-value logic signaling, and, upon detection of multi-value logic signaling on the first pin, to generate a signature activation signal.
12. The integrated circuit of claim 11 , wherein the multi-value logic receiver comprises a first comparator, which takes a first threshold voltage and a first input as inputs, and a second comparator, that takes a second threshold voltage and a second input as inputs.
13. The integrated circuit of claim 10 , wherein the activation portion comprises a signature detection circuit configured to receive the signature activation signal from the multi-value logic receiver, to monitor the second pin for a digital signal signature, and, upon detection of the digital signal signature, to generate the second function activation signal.
14. The integrated circuit of claim 13 , wherein the signature detection circuit comprises a quiescence detection element.
15. The integrated circuit of claim 13 , wherein the signature detection circuit comprises a password detection element.
16. The integrated circuit of claim 10 , wherein the second function circuit activates upon receiving the second function activation signal.
17. The integrated circuit of claim 10 , wherein the activation portion is further configured to monitor the first pin for multi-value logic signaling of deactivation, and subsequently to deactivate the second function circuit.
18. The integrated circuit of claim 10 , wherein the first function is clock generation.
19. The integrated circuit of claim 10 , wherein the first function circuit comprises a phase-locked loop.
20. The integrated circuit of claim 10 , further comprising a memory device.