Error detection and recovery in a shared pipeline
A pipelined processing device includes: a processor configured to receive a request to perform an operation; a plurality of processing controllers configured to receive at least one instruction associated with the operation, each of the plurality of processing controllers including a memory to store at least one instruction therein; a pipeline processor configured to receive and process the at least one instruction, the pipeline processor including shared error detection logic configured to detect a parity error in the at least one instruction as the at least one instruction is processed in a pipeline and generate an error signal; and a pipeline bus connected to each of the plurality of processing controllers and configured to communicate the error signal from the error detection logic.
1. A pipelined processing device, comprising:
a processor configured to receive a request to perform an operation, the processor comprising:
a plurality of processing controllers configured to receive at least one instruction associated with the operation, each of the plurality of processing controllers including a memory to store at least one instruction therein;
a pipeline processor configured to receive and process the at least one instruction, the pipeline processor including error detection logic shared by each of the plurality of processing controllers, the shared error detection logic configured to check each instruction that passes through the pipeline processor, and detect a parity error in the at least one instruction as the at least one instruction is processed in a pipeline and generate an error signal; and
a pipeline bus connected to each of the plurality of processing controllers and configured to communicate the error signal from the error detection logic.
2. The device of claim 1 , wherein the processor is configured to communicate a result of pipeline processing of the at least one instruction via the pipeline bus.
3. The device of claim 1 , wherein the error signal is configured to indicate a type of parity error.
4. The device of claim 3 , wherein the type of parity error includes an instruction field in which the parity error has occurred.
5. The device of claim 3 , wherein the error detection logic includes a codepoint associated with each type of parity error.
6. The device of claim 1 , wherein the processor includes a cache and the plurality of processing controllers include a plurality of cache controllers.
7. The device of claim 1 , wherein each of the plurality of processing controllers includes recovery logic configured to receive the error signal and perform recovery actions in response to the error signal.
8. A method of pipeline processing, the method comprising:
receiving a request to perform an operation at a processor;
sending at least one instruction associated with the operation to each of a plurality of processing controllers, each of the plurality of processing controllers including a memory to store at least one instruction therein;
receiving and processing the at least one instruction via a pipeline processor;
checking each instruction that passes through the pipeline processor and detecting a parity error occurring in the at least one instruction as the at least one instruction is processed in a pipeline by error detection logic shared by each of the plurality of processing controllers; and
generating an error signal indicating the parity error in the error detection logic and sending the error signal to a processing controller associated with the instruction via a pipeline bus.
9. The method of claim 8 , wherein the processor is configured to communicate a result of pipeline processing of the at least one instruction via the pipeline bus.
10. The method of claim 8 , wherein the error signal is configured to indicate a type of parity error.
11. The method of claim 10 , wherein the type of parity error includes an instruction field in which the parity error has occurred.
12. The method of claim 10 , wherein the error detection logic includes a codepoint associated with each type of parity error.
13. The method of claim 8 , wherein the processor includes a cache and the plurality of processing controllers include a plurality of cache controllers.
14. The method of claim 8 , further comprising receiving the error signal and performing recovery actions via recovery logic in the processing controller.
15. A computer program product for pipeline processing, comprising a non-transitory tangible storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method comprising:
receiving a request to perform an operation at a processor;
sending at least one instruction associated with the operation to each of a plurality of processing controllers, each of the plurality of processing controllers including a memory to store at least one instruction therein;
receiving and processing the at least one instruction via a pipeline processor;
checking each instruction that passes through the pipeline processor and detecting a parity error occurring in the at least one instruction as the at least one instruction is processed in a pipeline by error detection logic shared by each of the plurality of processing controllers; and
generating an error signal indicating the parity error in the error detection logic and sending the error signal to a processing controller associated with the instruction via a pipeline bus.
16. The computer program product of claim 15 , wherein the processor is configured to communicate a result of pipeline processing of the at least one instruction via the pipeline bus.
17. The computer program product of claim 15 , wherein the error signal is configured to indicate a type of parity error.
18. The computer program product of claim 17 , wherein the type of parity error includes an instruction field in which the parity error has occurred.
19. The computer program product of claim 17 , wherein the error detection logic includes a codepoint associated with each type of parity error.
20. The computer program product of claim 15 , wherein the processor includes a cache and the plurality of processing controllers include a plurality of cache controllers.