Non-volatile memory device having variable resistance element
A non-volatile memory device includes a lower molding layer, a horizontal interconnection line on the lower molding layer, an upper molding layer on the horizontal interconnection line, pillars extending vertically through the upper molding layer, the horizontal interconnection line, and the lower molding layer, and a buffer layer interposed between the pillars and the molding layers. The device also includes variable resistance material and a diode layer interposed between the pillars and the horizontal interconnection line.
1. A semiconductor device comprising:
a lower molding layer;
a horizontal interconnection line disposed on the lower molding layer;
an upper molding layer disposed on the horizontal interconnection line;
a pillar extending vertically through the upper molding layer, the horizontal interconnection line, and the lower molding layer;
a buffer layer interposed between the pillar and each of the lower and upper molding layers; and
variable resistance material and a diode layer interposed between the pillar and the horizontal interconnection line.
2. The device of claim 1 , wherein the diode layer comprises a metal oxide and has a composition different from that of the variable resistance material.
3. The device of claim 1 , wherein the diode layer covers sidewall surfaces and top and bottom surfaces of the horizontal interconnection line.
4. The device of claim 1 , wherein the variable resistance material is interposed between the pillar and the buffer layer.
5. The device of claim 4 , wherein the diode layer is interposed between the pillar and the variable resistance material.
6. The device of claim 4 , wherein the diode layer is interposed between the variable resistance material and the buffer layer.
7. The device of claim 1 , wherein a first segment of the buffer layer is interposed between the pillar and the lower molding layer, a second segment of the buffer layer is interposed between the pillar and the upper molding layer, and the diode layer is interposed between the first and second segments of the buffer layer.
8. The device of claim 7 , wherein each of the first and second segments of the buffer layer comprises silicon, and the diode layer comprises a silicide layer contacting each of the first and second segments of the buffer layer.
9. The device of claim 1 , wherein the buffer layer comprises silicon oxide or silicon.