IP Library Granted Patent US 8,526,605
Granted Patent B2
US 8,526,605 · App. 12/576,544 · Granted Sep 3, 2013

Data encryption to provide data security and memory cell bit wear leveling

Inventor: Donald Preston Matthews, Jr. (Longmont, CO)
Assignee: Seagate Technology LLC
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Quick Facts
Patent No.
US 8,526,605
App. No.
12/576,544
Granted
Sep 3, 2013
Kind
B2
Abstract

Method and apparatus for encrypting and storing data to provide data security and memory cell bit wear leveling. In accordance with various embodiments, input data are provided for writing to a target page of memory in a storage array. A seed value is derived from a count value indicative of a number of times a write access has occurred on the target page of memory. A block encryption routine is applied to the input data using the seed value to generate encrypted output data that are thereafter written to the target page.

Claims (29)

1. A method comprising:

providing input data to be written to a target page of memory in a storage array;

deriving a seed value in relation to a count of write accesses previously carried out upon the target page;

dividing the input data into a plural number N multi-bit blocks of M-bits each;

using the seed value to initiate block encryption of the N multi-bit blocks of input data to respectively form N multi-bit blocks of encrypted output data; and

writing the N multi-bit blocks of encrypted output data to the target page.

2. The method of claim 1 , wherein the array comprises a plurality of non-volatile memory cells arranged into rows and columns, and wherein the target page of memory comprises a selected row of said memory cells.

3. The method of claim 1 , wherein the count comprises a number of write operations that have been previously carried out to write data to the target page.

4. The method of claim 1 , wherein the count comprises a value stored as metadata in a metadata field in the target page.

5. The method of claim 1 , wherein the storage array comprises a plurality of pages of memory, wherein the method further comprises employing wear leveling at the page level, and wherein the target page comprises an available erased page in the array.

6. The method of claim 1 , wherein the seed value is a multi-bit block of data of M-bits in length.

7. The method of claim 1 , wherein the seed value is characterized as an initialization vector, and wherein the using step further comprises employing cipher block chaining (CBC) encryption to form the encoded output data.

8. The method of claim 1 , wherein the seed value is characterized as an initial tweak value, and wherein the using step comprises employing XTS mode (XOR/Encryption/XOR based encryption with ciphertext stealing) encryption to form the encoded output data.

9. The method of claim 1 , wherein the seed value is further formed in relation to a logical block address (LBA) associated with the input data.

10. The method of claim 1 , wherein the seed value is formed by encrypting the count value with a cipher.

11. The method of claim 1 , further comprising reading metadata stored in the target page to retrieve said count, and wherein the writing step further comprises writing updated metadata to the target page, the updated metadata comprising an updated count of write accesses performed upon the target page.

12. An apparatus comprising:

a buffer adapted to temporarily store input data to be written to a target page of memory in a storage array;

a seed value generation block which derives a seed value in relation to a count value indicative of a number of write accesses previously carried out upon the target page;

an encryption system which divides the input data into a plural number N multi-bit blocks and which uses the seed value to respectively encrypt the N multi-bit blocks of the input data to form N multi-bit blocks of encrypted output data; and

a write circuit that writes the N multi-bit blocks of encrypted output data to the target page.

13. The apparatus of claim 12 , wherein the write circuit further operates to concurrently write an updated count value to a metadata field of the target page during said writing of the encrypted output data.

14. The apparatus of claim 12 , wherein the count value comprises a number of erase operations that have been previously carried out to erase memory cells along the target page.

15. The apparatus of claim 12 , wherein the encryption system is characterized as a cipher block chaining (CBC) encryption system which divides the input data into N multi-bit blocks of M-bits, wherein the seed value is a multi-bit block of data of M-bits in length, and wherein the encryption system sequentially encrypts said N multi-bit blocks by logically combining a selected block from the N multi-bit blocks with the seed value to form an M-bit result, applying an encryption routine to the M-bit result using a cipher to provide an M-bit encoded block, logically combining the M-bit encoded block with a second selected block from the N multi-bit blocks to form a second M-bit result, and applying an encryption routine to the second M-bit result using a cipher to provide a second M-bit encoded block, wherein the second M-bit encoded block forms one of the N multi-bit blocks of encrypted output data.

16. The apparatus of claim 12 , wherein the encryption system is characterized as an XTS encryption (XOR/Encryption/XOR based encryption with ciphertext stealing) system which divides the input data into N multi-bit blocks of M-bits each, wherein the seed value is encrypted and combined with a primary element to form an initial tweak, and wherein the tweak is combined in an XOR/Encrypt/XOR sequence with the input data to form the N multi-bit blocks of encrypted output data.

17. The apparatus of claim 12 , wherein the seed value generation block encrypts the count value with a cipher to generate the seed value.

18. The apparatus of claim 12 , wherein each of the N multi-bit blocks of input data is M-bits in length, and each of the N multi-bit blocks of encrypted output data is M-bits in length.

19. The apparatus of claim 12 , wherein the seed value generation block and the encryption system are embodied by a programmable controller which uses associated programming steps stored in a memory location.

20. The apparatus of claim 12 , wherein the seed value comprises a multi-bit value of M-bits that is different each time input data are written to the target page to provide bit-level wear leveling of memory cells along the target page.

Assignments (3)
RELEASE OF SECURITY INTEREST Recorded Jul 23, 2025
From: THE BANK OF NOVA SCOTIA
To: SEAGATE TECHNOLOGY PUBLIC LIMITED COMPANY; SEAGATE TECHNOLOGY; SEAGATE TECHNOLOGY HDD HOLDINGS; I365 INC.; SEAGATE TECHNOLOGY LLC; SEAGATE TECHNOLOGY INTERNATIONAL; SEAGATE HDD CAYMAN; SEAGATE TECHNOLOGY (US) HOLDINGS, INC.
Reel/Frame 072193/0001 →
SECURITY AGREEMENT Recorded Mar 24, 2011
From: SEAGATE TECHNOLOGY LLC
To: THE BANK OF NOVA SCOTIA, AS ADMINISTRATIVE AGENT
Reel/Frame 026010/0350 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 9, 2009
From: MATTHEWS, DONALD PRESTON, JR
To: SEAGATE TECHNOLOGY LLC
Reel/Frame 023352/0484 →
Continuity (1)
Related Publication 20110085657A1 · Apr 14, 2011