Selective management controller authenticated access control to host mapped resources

1. An information handling system comprising:

a host mapped general purpose input output (GPIO) including a plurality of registers, wherein a first register includes a system service tag associate with the information handling system;

a shared memory;

a host processor in communication with the host mapped GPIO and with the shared memory, the host processor including a basic input output system;

a board management controller separate from the host processor and in communication with the host mapped GPIO and with the shared memory, the board management controller configured to control accessibility to the plurality of registers in the GPIO, and to control write accessibility of the shared memory based on a private key received from the basic input output system requesting accessibility to the plurality of registers and write accessibility of the shared memory, wherein the private key is based on the system service tag;

a cryptography engine in communication with the board management controller, the cryptography engine configured to authenticate the private key received from the board management controller; and

wherein the board management controller is further configured to provide accessibility to the host mapped GPIO and the write ability to the shared memory for a specific number of transactions of the basic input output system when the private key is authenticated.

2. The information handling system of claim 1 further comprising:

a keyboard controller style in communication with the board management controller, the keyboard controller style configured to pass the private key from the basic input output system to the board management controller.

3. The information handling system of claim 1 wherein the specific number of transactions of the basic input output system is a programmable number of transactions.

4. The information handling system of claim 1 wherein the board management controller provides accessibility to the host mapped GPIO and the write ability to the shared memory for a specific amount of time when the private key is authenticated.

5. The information handling system of claim 4 wherein the specific amount of time is a programmable amount of time.

6. The information handling system of claim 1 wherein the board management controller provides accessibility to the host mapped GPIO and the write ability to the shared memory until the basic input output system explicitly locks the host mapped GPIO and write protects the shared memory.

7. The information handling system of claim 1 wherein the plurality of registers is locked upon an end of a power-on self-test of the system.

8. The information handling system of claim 1 wherein the shared memory is write-protected upon an end of a power-on self-test.

9. An information handling system comprising:

a host mapped general purpose input output (GPIO) including a plurality of registers, wherein a first register includes a system service tag associated with the information handling system;

a shared memory;

a host processor in communication with the host mapped GPIO and with the shared memory, the host processor including a basic input output system;

a board management controller separate from the host processor and in communication with the host mapped GPIO and with the shared memory, the board management controller configured to operate as a proxy for the basic input output system, and to change an input/output state of one of the plurality of registers of the host mapped GPIO based on a state change request and to write data to the shared memory based on a write request received from the basic input output system and when a private key from the basic input output system is authenticated, wherein the private key is based on the system service tag; and

a cryptography engine in communication with the board management controller, the cryptography engine configured to authenticate the private key received from the board management controller.

10. The information handling system of claim 9 further comprising:

a keyboard controller style in communication with the board management controller, the keyboard controller style configured to pass the private key, the state change request, and the write request from the basic input output system to the board management controller.

11. The information handling system of claim 9 wherein the plurality of registers is locked upon an end of a power-on self-test of the system.

12. The information handling system of claim 9 wherein the shared memory is write-protected upon an end of a power-on self-test.

13. A method comprising:

detecting, at a host processor of an information handling system, at least one of an end of a power-on self-test and completion of a runtime write;

setting, by a board management controller of the information handling system, a host mapped general purpose input output (GPIO) register in a locked state in response to the end of the power-on self-test or to the completion of the runtime write, wherein the GPIO register includes a system service tag associated with the information handling system, and wherein the board management controller is separate from the host processor;

setting, by the board management controller, a shared memory to a write protected state in response to the end of the power-on self-test or to the completion of the runtime write;

receiving a first request to change an input/output state of the host mapped GPIO register, or a second request to write to the shared memory;

receiving, at the board management controller, a private key with the first request or with the second request, wherein the private key is received from a basic input output system of the host processor and is generated based upon the system service tag;

passing the private key to a cryptography engine;

receiving an indication that the private key is authenticated from the cryptography engine;

setting, by the board management controller, the host mapped GPIO register to an unlock state when the private key is authenticated; and

setting, by the board management controller, the shared memory to a full read and write accessible state when the private key is authenticated.

14. The method of claim 13 further comprising:

determining that a specific number of transactions have occurred;

setting the host mapped GPIO register in the locked state when the specific number of transactions have occurred; and

setting a shared memory to a write protected state when the specific number of transactions have occurred.

15. The method of claim 13 further comprising:

determining that a specific amount of time has occurred;

setting the host mapped GPIO register in the locked state when the specific amount of time has occurred; and

setting a shared memory to a write protected state when the specific amount of time has occurred.

16. The method of claim 13 wherein the host mapped GPIO register and the shared memory are located on a remote access controller.

17. The method of claim 13 wherein the authentication of the private key is performed on a remote access controller.

18. The method of claim 13 wherein the first request and the second request are received from the basic input output system.