IP Library Granted Patent US 8,530,303
Granted Patent B2
US 8,530,303 · App. 13/243,147 · Granted Sep 10, 2013

Method of fabricating semiconductor device

Inventors: Jin-Bum Kim (Seoul, KR); Chul-Sung Kim (Seongnam-si, KR); Yu-Gyun Shin (Seongnam-si, KR); Dae-Yong Kim (Yongin-si, KR); Joon-Gon Lee (Seoul, KR); Kwang-Young Lee (Suwon-si, KR)
Assignee: Samsung Electronics Co., Ltd.
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Quick Facts
Patent No.
US 8,530,303
App. No.
13/243,147
Granted
Sep 10, 2013
Kind
B2
Abstract

A method of fabricating a semiconductor includes providing a substrate having a first region and a second region defined therein, forming a first gate and a first source and drain region in the first region and forming a second gate and a second source and drain region in the second region, forming an epitaxial layer in the second source and drain region, forming a first metal silicide layer in the first source and drain region, forming an interlayer dielectric layer on the first region and the second region, forming a plurality of contact holes exposing the first metal silicide layer and the epitaxial layer while penetrating the interlayer dielectric layer, forming a second metal silicide layer in the exposed epitaxial layer, and forming a plurality of contacts contacting the first and second metal silicide layers by filling the plurality of contact holes.

Claims (23)

1. A method of fabricating a semiconductor device, comprising:

providing a substrate having a first region and a second region defined therein;

forming a first gate and a first source and drain region in the first region and forming a second gate and a second source and drain region in the second region;

forming an epitaxial layer in the second source and drain region;

forming a first metal silicide layer in the first source and drain region;

forming an interlayer dielectric layer on the first region and the second region;

forming a plurality of contact holes exposing the first metal silicide layer and the epitaxial layer by penetrating the interlayer dielectric layer;

forming a second metal silicide layer in the exposed epitaxial layer; and

forming a plurality of contacts contacting the first and second metal silicide layers by filling the plurality of contact holes.

2. The method of claim 1 , wherein the forming of the second metal silicide layer comprises forming the second metal silicide layer after forming the first metal silicide layer, the interlayer dielectric layer, and the plurality of contact holes.

3. The method of claim 1 , wherein the forming of the first metal silicide layer comprise performing at least two thermal processes on the substrate.

4. The method of claim 3 , wherein the performing of the at least two thermal processes comprises:

forming a blocking layer on the substrate in the second region;

forming a first metal layer contacting the first source and drain region on the substrate having the blocking layer;

selectively forming a first pre-metal silicide layer in the first source and drain region by performing a first thermal process; and

changing the first pre-metal silicide layer into the first metal silicide layer by performing a second thermal process at a higher temperature than the first thermal process.

5. The method of claim 4 , wherein the changing of the first pre-metal silicide layer into the first metal silicide layer comprises changing the first pre-metal silicide layer into the first metal silicide layer such that a proportion of silicon atoms relative to metal atoms of the first metal silicide layer is greater than a proportion of silicon atoms relative to metal atoms of the first pre-metal silicide layer.

6. The method of claim 1 , wherein the forming of the second metal silicide layer comprises:

forming a second metal layer contacting the exposed epitaxial layer; and

performing at least one thermal process on the substrate.

7. The method of claim 6 , wherein the performing of the at least one thermal process comprises:

forming a second pre-metal silicide layer on the exposed epitaxial layer by performing a first thermal process on the substrate having the second metal layer; and

changing the second pre-metal silicide layer into the second metal silicide layer by performing a second thermal process at a higher temperature than the first thermal process.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 23, 2011
From: KIM, JIN-BUM; KIM, CHUL-SUNG; SHIN, YU-GYUN; KIM, DAE-YONG; LEE, JOON-GON; LEE, KWANG-YOUNG
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 026961/0322 →
Priority Claims (1)
KR 10-2011-0001073 · Jan 5, 2011 · national
Continuity (1)
Related Publication 20120171826A1 · Jul 5, 2012