Semiconductor device
A semiconductor device includes a substrate, a gate structure, a source structure and a drain structure. The substrate includes a deep well region, and the gate structure is disposed on the deep well region. The source structure is formed within the deep well and located at a first side of the gate structure. The drain structure is formed within the deep well region and located at a second side of the gate structure. The drain structure includes a first doped region of a first conductivity type, a first electrode and a second doped region of a second conductivity type. The first doped region is located in the deep well region; the first electrode is electrically connected to the first doped region. The second doped region is disposed within the first doped region and between the first electrode and the gate structure.
1. A semiconductor device, comprising:
a substrate, having a deep well;
a gate structure, disposed above the deep well;
a source structure, disposed in the deep well, and located at a first side of the gate structure; and
a drain structure, disposed in the deep well, and located at a second side of the gate structure, wherein the drain structure comprises:
a first doped region of a first conductivity type, disposed in the deep well;
a first electrode, electrically connected to the first doped region; and
a second doped region of a second conductivity type, disposed in the first doped region and between the first electrode and the gate structure, wherein the deep well is a deep N type well, the first doped region comprises an N-grade region and a first N+ region, the first N+ regions is disposed in the N-grade region, the second doped region is a first P+ region comprising a plurality of isolated P+ sub-regions arranged in the first N+ region.
2. The semiconductor device of claim 1 , wherein the substrate is a silicon substrate.
3. The semiconductor device of claim 1 , wherein the source structure comprises:
a P type substrate region, located in the deep well;
a second N+ region, disposed in the P type substrate region;
a second electrode, electrically connected to the second N+ region; and
a second P+ region, disposed in the second N+ region.
4. The semiconductor device of claim 3 , wherein the first electrode is electrically connected to an anode for proving a working voltage, and the second electrode is electrically connected to a cathode for proving a grounding voltage.
5. The semiconductor device of claim 3 , wherein the first P+ region and the second P+ region have same dose and doping depth.
6. The semiconductor device of claim 1 , wherein the gate structure comprises a gate insulating layer and a gate conductor layer, and the gate insulating layer is interposed between the gate conductor layer and the deep well.
7. The semiconductor device of claim 1 , wherein the semiconductor device is formed in an ESD protecting circuit.
8. The semiconductor device of claim 1 , further comprising a guard ring disposed at a peripheral portion of the semiconductor device.
9. The semiconductor device of claim 1 , wherein the first conductivity type is different with the second conductivity type.