IP Library › Granted Patent US 8,533,942
Granted Patent B2
US 8,533,942 · App. 12/275,481 · Granted Sep 17, 2013

Production method of multilayer printed wiring board and multilayer printed wiring board

Inventors: Seiichiro Ohashi (Kawasaki, JP); Eiichi Hayashi (Kawasaki, JP); Shigeo Nakamura (Kawasaki, JP); Takaaki Yazawa (Nagano, JP); Junichi Nakamura (Nagano, JP)
Assignees: Ajinomoto Co., Inc.; Shinko Electric Industries Co., Ltd.
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Quick Facts
Patent No.
US 8,533,942
App. No.
12/275,481
Granted
Sep 17, 2013
Kind
B2
Abstract

Multilayer printed wiring boards may be prepared by forming a via hole by laser irradiation in insulating layer formed by a prepreg, comprised of a glass cloth impregnated with a thermosetting resin composition, and subjecting the via hole to a glass etching treatment with a glass etching solution and then to a desmear treatment with an oxidizing agent solution. By such a process, etch back phenomenon and excessive protrusion of glass cloth from the wall surface of a via hole can be sufficiently suppressed, and a highly reliable via can be formed. Particularly, a highly reliable via can be formed in a small via hole having a top diameter of 75 μm or below.

Claims (20)

1. A process for making a multilayer printed wiring board, comprising performing steps (i) through (v) in the order of from (i) to (v):

(i) forming an insulating layer by laminating a prepreg, said prepreg comprising a glass cloth impregnated with a thermosetting resin, on at least one surface of a circuit substrate having a conductive circuit on its surface;

(ii) forming, by laser irradiation, a via hole in said insulating layer, such that a said conductive circuit is exposed at the bottom of said via hole;

(iii) subjecting glass cloth projecting into said via hole to a glass etching treatment with a glass etching solution, to obtain a glass etching-treated via hole;

(iv) subjecting said glass etching-treated via hole to a desmear treatment with an oxidizing agent solution; and

(v) forming a via which is connected to said conductive circuit by said via hole.

2. The process of claim 1 , wherein said via hole has a top diameter of not more than 75 μm and not less than 60 μm.

3. The process of claim 1 , wherein said insulating layer is formed by a process comprising:

laminating said prepreg on at least one surface of said circuit substrate, to obtain a laminate;

heating and pressing said laminate under reduced pressure; and

thermally curing said prepreg.

4. The process of claim 1 , wherein said desmear treatment comprises treatment with an oxidizing agent solution which is an alkaline permanganate solution.

5. The process of claim 1 , wherein said desmear treatment is performed simultaneously with a roughening treatment of said insulating layer surface with said oxidizing agent solution.

6. The process of claim 5 , further comprising:

forming a conductive layer on a roughened surface of said insulating layer by plating.

7. The process of claim 6 , further comprising:

annealing said insulating layer and said conductive layer after forming said conductive layer.

8. The process of claim 7 , further comprising:

forming a circuit on said conductive layer.

9. The process of claim 1 , wherein said glass etching treatment in step (iii) is performed by etching the glass cloth from the via sidewall surface to the inside of the insulating layer, and said desmear treatment in step (iv) is performed such that the protrusion length of glass cloth from the sidewall of said via hole after said desmear treatment is not more than 6 μm.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 12, 2009
From: OHASHI, SEIICHIRO; HAYASHI, EIICHI; NAKAMURA, SHIGEO; YAZAWA, TAKAAKI; NAKAMURA, JUNICHI
To: AJINOMOTO CO., INC.; SHINKO ELECTRIC INDUSTRIES CO., LTD.
Reel/Frame 022250/0651 →
Priority Claims (1)
JP 2007-303737 · Nov 22, 2007 · national
Continuity (1)
Related Publication 20090133910A1 · May 28, 2009