Die up fully molded fan-out wafer level packaging

1. A method of manufacturing a semiconductor chip comprising:

placing a plurality of die units face up on a carrier, each die unit having an active front surface oriented away from the carrier and a back surface opposing the active front surface, the active front surface and the back surface joined by at least four side surfaces;

encapsulating the plurality of die units with an encapsulant that covers the active front surface and the four side surfaces of each of the plurality of die units in a single step while the plurality of die units are face up on the carrier; and

exposing, through removal of a portion of the encapsulant covering on the active front surface, at least one conductive interconnect that was coupled to a die bond pad before encapsulating the plurality of die units.

2. The method of claim 1 , wherein the encapsulant layer is a polymer layer.

3. The method of claim 2 , wherein the polymer layer is a dielectric film.

4. The method of claim 3 , wherein the dielectric film is an epoxy film positioned between the die units and a carrier.

5. The method of claim 4 , wherein applying the epoxy film comprises applying the epoxy film having substantially a same thickness as a thickness of the encapsulant covering the active surface after the conductive interconnect is exposed.

6. The method of claim 1 , wherein the at least one conductive interconnect is a plated copper post.

7. The method of claim 6 , wherein copper posts are plated over die bond pads on the active surface of the die units.

8. The method of claim 1 , wherein encapsulating the plurality of die units further comprises encapsulating through a compression molding process.

9. The method of claim 1 , wherein encapsulating the plurality of die units further comprises encapsulating through a lamination process.

10. The method of claim 1 , further comprising applying a fan-in redistribution layer to a native device wafer before encapsulating the plurality of die units.

11. The method of claim 10 , wherein the conductive interconnect is a plurality of copper posts plated over redistribution layer traces.

12. The method of claim 1 , further comprising curing the encapsulant layer.

13. The method of claim 1 , wherein the conductive interconnect further electrically couples to a fan-out redistribution layer.

14. The method of claim 1 , further comprising applying a dielectric film to a back surface of at least one of the die units.

15. The method of claim 1 , wherein the conductive interconnect has a height of at least about 20 microns.

16. A method of manufacturing a semiconductor chip comprising:

placing a plurality of die units face up on a carrier, each die unit having an active front surface and a back surface opposing the active front surface, the active front surface and the back surface joined by at least four side surfaces;

encapsulating the plurality of die units with an encapsulant covering the active front surface and the four side surfaces of each of the plurality of die units; and

exposing, through the encapsulant covering on the active front surface, at least one conductive interconnect electrically coupled to a die bond pad, wherein exposing the at least one conductive interconnect comprises adjusting a thickness of the encapsulant covering the active front surface of the die units by removing encapsulant until the thickness of the encapsulant covering the active front surface is between a ratio of 5:1 and 1:5 compared with a thickness of encapsulant on a back surface of the die units.

17. A wafer level package comprising:

a die unit having an active surface and a back surface opposing the active surface, the active surface and back surface joined by four side surfaces;

a single first encapsulant that covers the active surface and the four side surfaces of the die unit; and

a plurality of conductive interconnects electrically connecting a plurality of die bond pads on the active surface to a first redistribution layer.

18. The wafer level package of claim 17 , wherein the first redistribution layer is a fan-out redistribution layer.

19. The wafer level package of claim 17 , wherein the conductive interconnects are plated over traces of the redistribution layer.

20. The wafer level package of claim 17 , wherein the conductive interconnects are plated over die bond pads on the active surface of the die unit.

21. The wafer level package of claim 17 , further including a polymer layer disposed over the active surface.

22. The wafer level package of claim 21 , wherein the polymer layer is dielectric film.

23. The wafer level package of claim 22 , further comprising a second encapsulant disposed over the back surface of the die unit.

24. The wafer level package of claim 17 , wherein a thickness of the first encapsulant covering the active surface is substantially a same thickness as a thickness of a second encapsulant covering the back surface.

25. The wafer level package of claim 17 , wherein a thickness of the first encapsulant covering the active surface has a ratio of between approximately ⅕ and 5 in relation to a thickness of a second encapsulant covering the back surface.

26. The wafer level package of claim 17 , wherein the conductive interconnects have a height of at least about 20 microns.

27. The wafer level package of claim 17 , wherein the first encapsulant or a second encapsulant disposed over the back surface of the die unit comprises an epoxy film.