Semiconductor device
A semiconductor device of the present invention has a first-conductivity-type substrate having second-conductivity-type base regions exposed to a first surface thereof; trench gates provided to a first surface of the substrate; first-conductivity-type source regions formed shallower than the base regions; a plurality of second-conductivity-type column regions located between two adjacent trench gates in a plan view, while being spaced from each other in a second direction normal to the first direction; the center of each column region and the center of each base contact region fall on the center line between two trench gates; and has no column region formed below the trench gates.
1. A semiconductor device comprising:
a semiconductor layer of a first-conductivity-type formed on a semiconductor substrate;
first and second trench gates provided in an upper surface of the semiconductor layer, the first and second trench gates extending in parallel in a first direction in plan view and being disposed to be spaced from each other in a second direction perpendicular to the first direction in plan view;
a base region of a second-conductivity-type formed in an upper surface of the semiconductor layer so that the base region is sandwiched between the first and second trench gates in plan view, a depth of the base region being shallower than that of the first and second trench gates;
a source region of the first-conductivity-type formed in an upper surface of the base region so that at least a part of the source region is sandwiched between the first and second trench gates in plan view, a depth of the source region being shallower than that of the base region;
a plurality of base contact regions formed in the upper surface of the base region; and
a plurality of column regions of the second-conductivity-type formed in the semiconductor layer, each of the plurality of column regions being formed under the corresponding base contact region, respectively,
wherein a plurality of combinations, each of which comprises a corresponding one of the base contact region and the column region, are disposed between the first and second trench gates in plan view, the plurality of combinations being spaced from each other in the first direction in plan view, and
the plurality of column regions are not disposed directly below the first and second trench gates.
2. The semiconductor device as claimed in claim 1 , wherein, the base region and the plurality of column regions are connected mutually.
3. The semiconductor device as claimed in claim 1 , wherein, the base region and the plurality of column regions are separated from each other.
4. The semiconductor device as claimed in claim 1 , wherein each of the plurality of column regions is composed of a plurality of sub-column regions spaced from each other in a depth direction.
5. The semiconductor device as claimed in claim 1 , wherein the plurality of combinations are disposed substantially at a center line between the first and second trench gates in plan view.
6. The semiconductor device as claimed in claim 1 , wherein a plurality of openings are formed to be surrounded by the source region, each of the plurality of openings is disposed corresponding to each of the plurality of combinations in plan view.
7. The semiconductor device as claimed in claim 1 , wherein the source region is composed of a plurality of sub-source regions spaced from each other in the first direction so that one of the sub-source regions and one of the base contact regions are alternately disposed in the first direction in plan view.
8. The semiconductor device as claimed in claim 1 , wherein the plurality of column regions are not in contact with the semiconductor substrate.
9. The semiconductor device as claimed in claim 1 , wherein the plurality of column regions are in contact with the semiconductor substrate.