Granted Patent B2

US 8,536,925 · App. 12/598,352 · Granted Sep 17, 2013

Inventors: Dipankar Bhattacharya (Macungie, PA); Makeshwar Kothandaraman (Whitehall, PA); John C. Kriz (Palmerton, PA); Bernard L. Morris (Emmaus, PA); Jeffrey J. Nagy (Allentown, PA); Peter J. Nicholas (Philadelphia, PA)

Assignee: Agere Systems LLC

Abstract

Claims (45)

1. A voltage translator circuit, comprising:

an input stage adapted for receiving an input signal referenced to a first voltage supply;

a latch adapted for connection to a second voltage supply and operative to at least temporarily store a logic state of the input signal;

a voltage clamp coupled between the input stage and the latch, the voltage clamp being operative to set a maximum voltage across the latch to a first prescribed level and to set a maximum voltage across the input stage to a second prescribed level, the voltage translator circuit generating a first output signal at a junction between the latch and the voltage clamp, the voltage translator circuit generating a second output signal at a junction between the voltage clamp and the input stage; and

at least first and second output buffers, the first output buffer being operative to receive the first output signal and to generate a first buffered output signal indicative thereof, the second output buffer being operative to receive the second output signal and to generate a second buffered output signal indicative thereof, the first buffered output signal being referenced to the second voltage supply of the voltage translator circuit and to a first bias voltage, the second buffered output signal being referenced to a voltage return of the voltage translator circuit and to a second bias voltage; and

wherein the first buffered output signal swings between the second voltage supply of the voltage translator circuit and the first bias voltage, and the second buffered output signal swings between the voltage return of the voltage translator circuit and the second bias voltage.

2. The voltage translator circuit of claim 1 ,

wherein each of the input stage, the latch and the voltage clamp comprises at least one thick oxide transistor.

3. The voltage translator circuit of claim 1 , wherein the input stage comprises a pair of transistors connected in a differential input stage configuration.

4. The voltage translator circuit of claim 1 , wherein the input stage comprises first and second NMOS transistors, a first source/drain of the first NMOS transistor being adapted for connection to a voltage return of the voltage translator circuit, a second source/drain of the first NMOS transistor being connected to a first node of the voltage clamp, a gate of the first NMOS transistor being adapted for receiving a first signal indicative of a logical complement of the input signal, a first source/drain of the second NMOS transistor being adapted for connection to the voltage return of the voltage translator circuit, a second source/drain of the second NMOS transistor being connected to a second node of the voltage clamp, and a gate of the second NMOS transistor being adapted for receiving a second signal indicative of the input signal.

5. The voltage translator circuit of claim 1 , wherein the latch comprises first and second PMOS transistors, a first source/drain of the first PMOS transistor being adapted for connection to a second voltage supply of the voltage translator circuit, a second source/drain of the first PMOS transistor being connected to the voltage clamp at a third node, a gate of the first PMOS transistor being connected to the voltage clamp at a fourth node, a first source/drain of the second PMOS transistor being adapted for connection to the second voltage supply of the voltage translator circuit, a second source/drain of the second PMOS transistor being connected to the voltage clamp at the fourth node, and a gate of the second PMOS transistor being connected to the voltage clamp at the third node.

6. The voltage translator circuit of claim 1 , wherein the voltage clamp comprises first and second PMOS transistors and first and second NMOS transistors, a first source/drain of the first and second PMOS transistors being connected to first and second nodes, respectively, of the latch, gates of the first and second PMOS transistors being connected together and adapted to receive a first bias voltage, a second source/drain of the first PMOS transistor being connected to a first source/drain of the first NMOS transistor, a second source/drain of the second PMOS transistor being connected to a first source/drain of the second NMOS transistor, gates of the first and second NMOS transistors being connected together and adapted to receive a second bias voltage, and a second source/drain of the first and second NMOS transistors being connected to first and second nodes, respectively, of the input stage.

7. The voltage translator circuit of claim 6 , wherein the first and second bias voltages are substantially equal to one another.

8. The voltage translator circuit of claim 1 , wherein the first prescribed level is controlled as a function of the first bias voltage, and the second prescribed level is controlled as a function of the second bias voltage.

9. The voltage translator circuit of claim 1 , further comprising at least third and fourth output buffers, the third output buffer being operative to receive a logical complement of the first output signal and to generate a third buffered output signal indicative thereof, the fourth output buffer being operative to receive a logical complement of the second output signal and to generate a fourth buffered output signal indicative thereof, the third buffered output signal being referenced to the second voltage supply of the voltage translator circuit and to the first bias voltage, the fourth buffered output signal being referenced to the voltage return of the voltage translator circuit and to the second bias voltage.

10. The voltage translator circuit of claim 9 , further comprising at least one output latch coupled to the voltage clamp and operative to at least temporarily store a logic state of one or more of the output signals generated by the voltage translator circuit.

11. The voltage translator circuit of claim 10 , wherein the at least one output latch comprises first and second inverters coupled together in a cross-coupled configuration in which an input of the first inverter is coupled to an output of the second inverter and is adapted to receive the fourth buffered output signal and an input of the second inverter is coupled to an output of the first inverter and is adapted to receive the second buffered output signal, and wherein the first and second inverters are referenced to the second voltage supply of the voltage translator circuit and to the first bias voltage.

12. The voltage translator circuit of claim 10 , wherein the at least one output latch comprises first and second inverters coupled together in a cross-coupled configuration in which an input of the first inverter is coupled to an output of the second inverter and is adapted to receive the third buffered output signal and an input of the second inverter is coupled to an output of the first inverter and is adapted to receive the first buffered output signal, and wherein the first and second inverters are referenced to the second bias voltage and to the voltage return of the voltage translator circuit.

13. The voltage translator circuit of claim 1 , wherein the first bias voltage and the second bias voltage are driven to different voltage levels as a function of the second voltage supply and first voltage supply, respectively.

14. A buffer circuit, comprising:

at least one voltage translator circuit, the voltage level translator including:

an input stage adapted for receiving an input signal referenced to a first voltage supply;

a latch adapted for connection to a second voltage supply and operative to at least temporarily store a logic state of the input signal; and

a voltage clamp coupled between the input stage and the latch, the voltage clamp being operative to set a maximum voltage across the latch to a first prescribed level and to set a maximum voltage across the input stage to a second prescribed level, the voltage translator circuit generating a first output signal at a junction between the latch and the voltage clamp, the voltage translator circuit generating a second output signal at a junction between the voltage clamp and the input stage;

a first pre-driver circuit coupled to the at least one voltage translator circuit, the first pre-driver circuit being operative to receive the first output signal and to generate a first control signal as a function thereof, wherein the first pre-driver circuit is referenced to a second voltage supply of the voltage translator circuit and to a first bias voltage;

a second pre-driver circuit coupled to the at least one voltage translator circuit, the second pre-driver circuit being operative to receive the second output signal and to generate a second control signal as a function thereof, wherein the second pre-driver circuit is referenced to a voltage return of the voltage translator circuit and to a second bias voltage;

wherein the first control signal swings between the second voltage supply of the voltage translator circuit and the first bias voltage, and the second control signal swings between the voltage return of the voltage translator circuit and the second bias voltage; and

an output stage coupled to the first and second pre-driver circuits, the output stage including at least a first pull-up device adapted for connection between the second voltage supply of the voltage translator circuit and an input/output pad of the buffer circuit, and at least one pull-down device adapted for connection between a voltage return of the voltage translator circuit and the input/output pad.

15. An integrated circuit including at least one voltage translator circuit, the at least one voltage translator circuit comprising:

an input stage adapted for receiving an input signal referenced to a first voltage supply;

a latch adapted for connection to a second voltage supply and operative to at least temporarily store a logic state of the input signal;

a voltage clamp coupled between the input stage and the latch, the voltage clamp being operative to set a maximum voltage across the latch to a first prescribed level and to set a maximum voltage across the input stage to a second prescribed level, the voltage translator circuit generating a first output signal at a junction between the latch and the voltage clamp, the voltage translator circuit generating a second output signal at a junction between the voltage clamp and the input stage; and

at least first and second output buffers, the first output buffer being operative to receive the first output signal and to generate a first buffered output signal indicative thereof, the second output buffer being operative to receive the second output signal and to generate a second buffered output signal indicative thereof, the first buffered output signal being referenced to a second voltage supply of the voltage translator circuit and to a first bias voltage, the second buffered output signal being referenced to a voltage return of the voltage translator circuit and to a second bias voltage; and

wherein the first buffered output signal swings between the second voltage supply of the voltage translator circuit and the first bias voltage, and the second buffered output signal swings between the voltage return of the voltage translator circuit and the second bias voltage.

16. The integrated circuit of claim 15 , wherein the voltage clamp comprises first and second PMOS transistors and first and second NMOS transistors, a first source/drain of the first and second PMOS transistors being connected to first and second nodes, respectively, of the latch, gates of the first and second PMOS transistors being connected together and adapted to receive a first bias voltage, a second source/drain of the first PMOS transistor being connected to a first source/drain of the first NMOS transistor, a second source/drain of the second PMOS transistor being connected to a first source/drain of the second NMOS transistor, gates of the first and second NMOS transistors being connected together and adapted to receive a second bias voltage, and a second source/drain of the first and second NMOS transistors being connected to first and second nodes, respectively, of the input stage.

17. The integrated circuit of claim 16 , wherein the first and second bias voltages are substantially equal to one another.

18. The integrated circuit of claim 15 , wherein the first prescribed level is controlled as a function of the first bias voltage, and the second prescribed level is controlled as a function of the second bias voltage.

19. The integrated circuit of claim 15 , wherein the at least one voltage translator circuit further comprises at least third and fourth output buffers, the third output buffer being operative to receive a logical complement of the first output signal and to generate a third buffered output signal indicative thereof, the fourth output buffer being operative to receive a logical complement of the second output signal and to generate a fourth buffered output signal indicative thereof, the third buffered output signal being referenced to the second voltage supply of the voltage translator circuit and to the first bias voltage, the fourth buffered output signal being referenced to the voltage return of the voltage translator circuit and to the second bias voltage.

20. An electronic system, comprising:

at least one integrated circuit adapted to perform voltage level translation, the at least one integrated circuit including at least one voltage translator circuit comprising:

an input stage adapted for receiving an input signal referenced to a first voltage supply;

a latch adapted for connection to a second voltage supply and operative to at least temporarily store a logic state of the input signal;

a voltage clamp coupled between the input stage and the latch, the voltage clamp being operative to set a maximum voltage across the latch to a first prescribed level and to set a maximum voltage across the input stage to a second prescribed level, the voltage translator circuit generating a first output signal at a junction between the latch and the voltage clamp, the voltage translator circuit generating a second output signal at a junction between the voltage clamp and the input stage; and

at least first and second output buffers, the first output buffer being operative to receive the first output signal and to generate a first buffered output signal indicative thereof, the second output buffer being operative to receive the second output signal and to generate a second buffered output signal indicative thereof, the first buffered output signal being referenced to a second voltage supply of the voltage translator circuit and to a first bias voltage, the second buffered output signal being referenced to a voltage return of the voltage translator circuit and to a second bias voltage; and

wherein the first buffered output signal swings between the second voltage supply of the voltage translator circuit and the first bias voltage, and the second buffered output signal swings between the voltage return of the voltage translator circuit and the second bias voltage.

Assignments (10)

Continuity (1)